On Wed, 06 Feb 2013, Jani Nikula <jani.nikula at linux.intel.com> wrote: > On Sat, 02 Feb 2013, Jesse Barnes <jbarnes at virtuousgeek.org> wrote: >> Add a few regs needed for various clock gating init purposes and make >> sure they don't fall into the display offset range on VLV. > > GEN7_UCGCTL4 needs to be fixed in i915_reg.h after IS_DISPLAYREG > removal. Strike that. The whole patch can be dropped since it's not a display reg. > >> >> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org> >> --- >> drivers/gpu/drm/i915/i915_drv.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c >> index 69d0637..13b9b4f 100644 >> --- a/drivers/gpu/drm/i915/i915_drv.c >> +++ b/drivers/gpu/drm/i915/i915_drv.c >> @@ -1208,6 +1208,7 @@ static bool IS_DISPLAYREG(u32 reg) >> case GEN7_HALF_SLICE_CHICKEN1: >> case GEN6_MBCTL: >> case GEN6_UCGCTL2: >> + case GEN7_UCGCTL4: >> return false; >> default: >> break; >> -- >> 1.7.9.5 >> >> _______________________________________________ >> Intel-gfx mailing list >> Intel-gfx at lists.freedesktop.org >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
