With the PTE poking code pulled into i915, we need to make sure we don't add the display offset to our TLB flush writes. Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org> --- drivers/gpu/drm/i915/i915_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 28d5992..dde54b1 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1212,6 +1212,7 @@ static bool IS_DISPLAYREG(u32 reg) case FORCEWAKE_VLV: case FORCEWAKE_ACK_VLV: case VLV_GTLC_WAKE_CTRL: + case GFX_FLSH_CNTL_GEN6: return false; default: break; -- 1.7.9.5
