On Fri, Jan 25, 2013 at 09:44:48PM +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrj?l? <ville.syrjala at linux.intel.com>
>
> From BSpec / SR01 - Clocking Mode:
> "The following sequence must be used when disabling the VGA plane.
> Write SR01 to set bit 5 = 1 to disable video output.
> Wait for 100us.
> Disable the VGA plane via Bit 31 of the MMIO VGA control."
>
> So simply call i915_disable_vga() from i915_redisable_vga().
>
> Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com>
Ok, merged the last 3 pieces of this series now, thanks for the patches.
I've punted on the don't touch VGA0, ... on gen5+ patch, since that's now
only relevant for ums (and I've been too lazy to dig out the docs).
-Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e96ac19..6cc5700 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8934,8 +8934,7 @@ void i915_redisable_vga(struct drm_device *dev)
>
> if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
> DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
> - I915_WRITE(vga_reg, VGA_DISP_DISABLE);
> - POSTING_READ(vga_reg);
> + i915_disable_vga(dev);
> }
> }
>
> --
> 1.7.12.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
