On Tue, Jan 29, 2013 at 04:35:18PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> The DP_TP_STATUS register for PORT_A doesn't exist. Our documentation
> will be fixed soon, so the code does not match it for now.
>
> This solves "Timed out waiting for DP idle patterns" and "unclaimed
> register" messages on eDP.
>
> V1: Was called "drm/i915: don't read DP_TP_STATUS(PORT_A)"
> V2: Was called "drm/i915: don't send DP idle pattern before normal
> pattern on HSW"
> V3: Only change the code that touches PORT_A.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 16 ++++++++++------
> 1 file changed, 10 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 51fd797..1b76b04 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1785,14 +1785,18 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> case DP_TRAINING_PATTERN_DISABLE:
> - temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
> - I915_WRITE(DP_TP_CTL(port), temp);
>
> - if (wait_for((I915_READ(DP_TP_STATUS(port)) &
> - DP_TP_STATUS_IDLE_DONE), 1))
> - DRM_ERROR("Timed out waiting for DP idle patterns\n");
> + if (port != PORT_A) {
> + temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
> + I915_WRITE(DP_TP_CTL(port), temp);
> +
> + if (wait_for((I915_READ(DP_TP_STATUS(port)) &
> + DP_TP_STATUS_IDLE_DONE), 1))
> + DRM_ERROR("Timed out waiting for DP idle patterns\n");
I checkpatch complained about the long line, and I count about 5 levels of
indentation. The function is also growing a bit long in lines. Can you
please cut out per-platform helpers or something like that as a follow-up?
Queued for -next, thanks for the patch.
-Daniel
> +
> + temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> + }
>
> - temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
> temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
>
> break;
> --
> 1.7.10.4
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
