Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> On Wed, Jan 30, 2013 at 12:59 PM, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > We may not concurrently change the power wells code. Which > is already guaranteed since modesets aren't concurrent. That > leaves races against setup/teardown/suspend/resume, and for > those we already (try) rather hard not to hit concurrent > modesets. > > No debug WARN_ON added since that would require us to grab the > modeset locks in init/suspend code. Which is again just cargo > culting since just grabbing the locks in those paths isn't good > enough, we need the right order of operations, too. > > Cc: Paulo Zanoni <paulo.r.zanoni at intel.com> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ---- > 1 file changed, 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 703219c..f024e7d 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4091,8 +4091,6 @@ void intel_init_power_well(struct drm_device *dev) > if (!IS_HASWELL(dev)) > return; > > - mutex_lock(&dev->struct_mutex); > - > /* For now, we need the power well to be always enabled. */ > intel_set_power_well(dev, true); > > @@ -4100,8 +4098,6 @@ void intel_init_power_well(struct drm_device *dev) > * the driver is in charge now. */ > if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) > I915_WRITE(HSW_PWR_WELL_BIOS, 0); > - > - mutex_unlock(&dev->struct_mutex); > } > > /* Set up chip specific power management-related functions */ > -- > 1.7.10.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Rodrigo Vivi Blog: http://blog.vivi.eng.br
