[PATCH v2 1/2] drm/i915/dp: Helper for checking DDI_BUF_CTL Idle status

[Manasi Navare <manasi.d.navare@xxxxxxxxx>]

Modify the helper to add a fixed delay or poll with timeout
based on platform specification in bothe enable and disable
cases so check for either Idle bit set (DDI_BUF_CTL is idle
for disable case) or check for Idle bit = 0 (non idle for
DDI BUF enable case)

Cc: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Cc: Imre Deak <imre.deak@xxxxxxxxx>
Signed-off-by: Manasi Navare <manasi.d.navare@xxxxxxxxx>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 34 +++++++++++++++---------
 1 file changed, 21 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ca7bb2294d2b..e4738c3b6d44 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -1182,18 +1182,26 @@ static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 }
 
 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
-				    enum port port)
+				    enum port port, bool idle)
 {
-	i915_reg_t reg = DDI_BUF_CTL(port);
-	int i;
-
-	for (i = 0; i < 16; i++) {
-		udelay(1);
-		if (intel_de_read(dev_priv, reg) & DDI_BUF_IS_IDLE)
-			return;
+	if (idle) {
+		if (IS_BROXTON(dev_priv))
+			udelay(16);
+		else
+			if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+					 DDI_BUF_IS_IDLE), 16))
+				drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
+					port_name(port));
+	} else {
+		if (INTEL_GEN(dev_priv) < 10)
+			udelay(600);
+		else
+			if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+					  DDI_BUF_IS_IDLE), 600))
+				drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
+					port_name(port));
 	}
-	drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c idle bit\n",
-		port_name(port));
+
 }
 
 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
@@ -1373,7 +1381,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder,
 		intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
 		intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
 
-		intel_wait_ddi_buf_idle(dev_priv, PORT_E);
+		intel_wait_ddi_buf_idle(dev_priv, PORT_E, true);
 
 		/* Reset FDI_RX_MISC pwrdn lanes */
 		temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
@@ -3495,7 +3503,7 @@ static void intel_disable_ddi_buf(struct intel_encoder *encoder,
 	intel_ddi_disable_fec_state(encoder, crtc_state);
 
 	if (wait)
-		intel_wait_ddi_buf_idle(dev_priv, port);
+		intel_wait_ddi_buf_idle(dev_priv, port, true);
 }
 
 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
@@ -4004,7 +4012,7 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
 		intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
 
 		if (wait)
-			intel_wait_ddi_buf_idle(dev_priv, port);
+			intel_wait_ddi_buf_idle(dev_priv, port, true);
 	}
 
 	dp_tp_ctl = DP_TP_CTL_ENABLE |
-- 
2.19.1

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