On Thu, Jan 24, 2013 at 11:41:53PM +0100, Daniel Vetter wrote: > On Thu, Jan 24, 2013 at 03:29:50PM +0200, ville.syrjala at linux.intel.com wrote: > > From: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > > > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 1c1e7f8..c3d4ddc 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -922,8 +922,8 @@ > > #define VGA1_PD_P1_DIV_2 (1 << 13) > > #define VGA1_PD_P1_SHIFT 8 > > #define VGA1_PD_P1_MASK (0x1f << 8) > > -#define _DPLL_A 0x06014 > > -#define _DPLL_B 0x06018 > > +#define _DPLL_A (dev_priv->info->display_mmio_offset + 0x6014) > > +#define _DPLL_B (dev_priv->info->display_mmio_offset + 0x6018) > > #define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B) > > #define DPLL_VCO_ENABLE (1 << 31) > > #define DPLL_DVO_HIGH_SPEED (1 << 30) > > @@ -982,7 +982,7 @@ > > #define SDVO_MULTIPLIER_MASK 0x000000ff > > #define SDVO_MULTIPLIER_SHIFT_HIRES 4 > > #define SDVO_MULTIPLIER_SHIFT_VGA 0 > > -#define _DPLL_A_MD 0x0601c /* 965+ only */ > > +#define _DPLL_A_MD (dev_priv->info->display_mmio_offset + 0x601c) /* 965+ only */ > > /* > > * UDI pixel divider, controlling how many pixels are stuffed into a packet. > > * > > @@ -1019,7 +1019,7 @@ > > */ > > #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f > > #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 > > -#define _DPLL_B_MD 0x06020 /* 965+ only */ > > +#define _DPLL_B_MD (dev_priv->info->display_mmio_offset + 0x6020) /* 965+ only */ > > #define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD) > > > > #define _FPA0 0x06040 > > @@ -1047,12 +1047,12 @@ > > #define DPLLA_TEST_N_BYPASS (1 << 3) > > #define DPLLA_TEST_M_BYPASS (1 << 2) > > #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) > > -#define D_STATE 0x6104 > > +#define D_STATE (dev_priv->info->display_mmio_offset + 0x6104) > > I only see this one here used in gen2/3 code ... > > > #define DSTATE_GFX_RESET_I830 (1<<6) > > #define DSTATE_PLL_D3_OFF (1<<3) > > #define DSTATE_GFX_CLOCK_GATING (1<<1) > > #define DSTATE_DOT_CLOCK_GATING (1<<0) > > -#define DSPCLK_GATE_D 0x6200 > > +#define DSPCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6200) > > This one here seems to be only used up to gen4 ... DSPCLK_GATE_D is used in intel_i2c_quirk_set(). OTOH gma500 has the same code commented out, so it may be that we can skip it too. Anyone have more details on this quirk? gma500 also seems to use DSPCLK_GATE_D to disable clock gating for some DP stuff on CDV. Considering the lineage we need to find out if that's something that affects VLV as well. > > # define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */ > > # define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */ > > # define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */ > > @@ -1159,7 +1159,7 @@ > > #define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9) > > #define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7) > > #define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6) > > -#define RAMCLK_GATE_D 0x6210 /* CRL only */ > > +#define RAMCLK_GATE_D (dev_priv->info->display_mmio_offset + 0x6210) /* CRL only */ > > And same here. Do we need those in vlv code, or can we just drop them for > now? I think D_STATE and RAMCLK_GATE_D can be dropped. We can convert them if and when we actaully have to touch them. -- Ville Syrj?l? Intel OTC
