On Fri, 18 Jan 2013, Paulo Zanoni <przanoni at gmail.com> wrote:
> From: Daniel Vetter <daniel.vetter at ffwll.ch>
>
> We can disable (almost) all the display hw if we only use pipe A, with
> the integrated edp transcoder on port A. Because we don't set the cpu
> transcoder that early (yet), we need to help us with a trick to simply
> check for any edp encoders.
>
> And wrt the old code: Can anyone explain what that struct mutex
> grabbing was supposed to protect?
>
> v2: Paulo Zanoni pointed out that we also need to configure the eDP
> cpu transcoder correctly.
>
> v3: Made by Paulo Zanoni
> - Rebase patch to be on top of "fix intel_init_power_wells" patch
> - Fix typos
> - Fix a small bug by adding a "connectors_active" check
> - Restore the initial code that unconditionally enables the power
> well when taking over from the BIOS
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 8 +++++++-
> drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 2 +-
> 4 files changed, 40 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 2e904a5..a4dd55a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -987,7 +987,13 @@ void intel_ddi_enable_pipe_func(struct drm_crtc *crtc)
> if (cpu_transcoder == TRANSCODER_EDP) {
> switch (pipe) {
> case PIPE_A:
> - temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> + /* Can only use the always-on power well for eDP when
> + * not using the panel fitter, and when not using motion
> + * blur mitigation (which we don't support). */
> + if (dev_priv->pch_pf_size)
> + temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
> + else
> + temp |= TRANS_DDI_EDP_INPUT_A_ON;
> break;
> case PIPE_B:
> temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 4a9f048..a7fb7e1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5595,6 +5595,35 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> return fdi_config_ok ? ret : -EINVAL;
> }
>
> +static void haswell_modeset_global_resources(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + bool enable = false;
> + struct intel_crtc *crtc;
> + struct intel_encoder *encoder;
> +
> + list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
> + if (crtc->pipe != PIPE_A && crtc->base.enabled)
> + enable = true;
> + /* XXX: Should check for edp transcoder here, but thanks to init
> + * sequence that's not yet availble. Just in case desktop eDP on
> + * PORT D is possible on haswell, too. */
Obligatory nitpick on something: s/availble/available/
Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> + }
> +
> + list_for_each_entry(encoder, &dev->mode_config.encoder_list,
> + base.head) {
> + if (encoder->type != INTEL_OUTPUT_EDP &&
> + encoder->connectors_active)
> + enable = true;
> + }
> +
> + /* Even the eDP panel fitter is outside the always-on well. */
> + if (dev_priv->pch_pf_size)
> + enable = true;
> +
> + intel_set_power_well(dev, enable);
> +}
> +
> static int haswell_crtc_mode_set(struct drm_crtc *crtc,
> struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode,
> @@ -8477,6 +8506,8 @@ static void intel_init_display(struct drm_device *dev)
> } else if (IS_HASWELL(dev)) {
> dev_priv->display.fdi_link_train = hsw_fdi_link_train;
> dev_priv->display.write_eld = haswell_write_eld;
> + dev_priv->display.modeset_global_resources =
> + haswell_modeset_global_resources;
> }
> } else if (IS_G4X(dev)) {
> dev_priv->display.write_eld = g4x_write_eld;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 8cfad75..7cea8e2 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -667,6 +667,7 @@ extern void intel_gpu_ips_init(struct drm_i915_private *dev_priv);
> extern void intel_gpu_ips_teardown(void);
>
> extern void intel_init_power_well(struct drm_device *dev);
> +extern void intel_set_power_well(struct drm_device *dev, bool enable);
> extern void intel_enable_gt_powersave(struct drm_device *dev);
> extern void intel_disable_gt_powersave(struct drm_device *dev);
> extern void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 2273b9c..9a4f754 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4043,7 +4043,7 @@ void intel_init_clock_gating(struct drm_device *dev)
> dev_priv->display.init_clock_gating(dev);
> }
>
> -static void intel_set_power_well(struct drm_device *dev, bool enable)
> +void intel_set_power_well(struct drm_device *dev, bool enable)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> bool is_enabled, enable_requested;
> --
> 1.7.10.4
>
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