On Sun, 2013-01-20 at 17:08 +0000, Chris Wilson wrote:
> During the initial bringup of IVB, we set the invalidation control to
> the pre-IVB default of always invalidating TLBs on every flush:
>
> commit b095cd0a0ccdbc00c9fd99d90b22f8563687971f
> Author: Jesse Barnes <jbarnes at virtuousgeek.org>
> Date: Fri Aug 12 15:28:32 2011 -0700
>
> drm/i915: set GFX_MODE to pre-Ivybridge default value even on Ivybridge
>
> We now have the required invalidates in place, so enable the
> optimisation and avoid the unnecessary flushes when we use pipe controls
> inside batches.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Reviewed-by: Imre Deak <imre.deak at intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index ae816fb..2d6d220 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -520,7 +520,7 @@ static int init_render_ring(struct intel_ring_buffer *ring)
>
> if (IS_GEN7(dev))
> I915_WRITE(GFX_MODE_GEN7,
> - _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> + _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS) |
> _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
>
> if (INTEL_INFO(dev)->gen >= 5) {
