On Fri, Jan 18, 2013 at 06:29:08PM -0200, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> If the power well is disabled, we should not try to read its
> registers, otherwise we'll get "unclaimed register" messages.
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a7fb7e1..921b020 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1214,9 +1214,15 @@ void assert_pipe(struct drm_i915_private *dev_priv,
> if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
> state = true;
>
> - reg = PIPECONF(cpu_transcoder);
> - val = I915_READ(reg);
> - cur_state = !!(val & PIPECONF_ENABLE);
> + if (cpu_transcoder == TRANSCODER_EDP ||
> + (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE)) {
Should that also check HSW_PWR_WELL_ENABLE? KVMR might have the well
enabled, while the driver has it disabled. But KVMR might have already
disabled the well, and it might get disabled just after this check,
and then you would hit the unclaimed register issue again.
> + reg = PIPECONF(cpu_transcoder);
> + val = I915_READ(reg);
> + cur_state = !!(val & PIPECONF_ENABLE);
> + } else {
> + cur_state = false;
> + }
> +
> WARN(cur_state != state,
> "pipe %c assertion failure (expected %s, current %s)\n",
> pipe_name(pipe), state_string(state), state_string(cur_state));
> --
> 1.7.10.4
>
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--
Ville Syrj?l?
Intel OTC
