For Gen11+ platforms BSpec suggests disabling specific QGV points separately, depending on bandwidth limitations and current display configuration. Thus it required adding a new PCode request for disabling QGV points and some refactoring of already existing SAGV code. Also had to refactor intel_can_enable_sagv function, as current seems to be outdated and using skl specific workarounds, also not following BSpec for Gen11+. v25: Rebased patch series as part was merged already v26: Had to resend the whole series as one more mid patch was added Stanislav Lisovskiy (9): drm/i915: Introduce skl_plane_wm_level accessor. drm/i915: Use bw state for per crtc SAGV evaluation drm/i915: Track active_pipes in bw_state drm/i915: Separate icl and skl SAGV checking drm/i915: Add TGL+ SAGV support drm/i915: Added required new PCode commands drm/i915: Rename bw_state to new_bw_state drm/i915: Restrict qgv points which don't have enough bandwidth. drm/i915: Enable SAGV support for Gen12 drivers/gpu/drm/i915/display/intel_bw.c | 163 ++++--- drivers/gpu/drm/i915/display/intel_bw.h | 18 + drivers/gpu/drm/i915/display/intel_display.c | 8 +- .../drm/i915/display/intel_display_types.h | 6 + drivers/gpu/drm/i915/i915_reg.h | 5 + drivers/gpu/drm/i915/intel_pm.c | 399 +++++++++++++++--- drivers/gpu/drm/i915/intel_pm.h | 5 +- drivers/gpu/drm/i915/intel_sideband.c | 2 + 8 files changed, 506 insertions(+), 100 deletions(-) -- 2.24.1.485.gad05a3d8e5 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
