Hi 2013/1/11 Rodrigo Vivi <rodrigo.vivi at gmail.com>: > From: Shobhit Kumar <shobhit.kumar at intel.com> > > v2: Add support for psr perfromance counter register and corrected > register names to reflect they are PSR registers. Also added bit > definitions for the registers > > v3: Add missing CDCLK_FREQ register needed for PSR enabling. > > Signed-off-by: Sateesh Kavuri <sateesh.kavuri at intel.com> > Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 47 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5b3020f..61de724 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1561,6 +1561,40 @@ > #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) > #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) > > +/* HSW eDP PSR registers */ > +#define EDP_PSR_CTL 0x64800 > +#define EDP_PSR_ENABLE (1<<31) > +#define EDP_PSR_LINK_DISABLE (0<<27) > +#define EDP_PSR_LINK_STANDBY (1<<27) > +#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25) > +#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25) > +#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25) > +#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25) > +#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25) > +#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20 Or you could also do something like: #define EDP_PSR_MAX_SLEEP_TIME(x) ((x) << 20) And maybe also #define EDP_PSR_MAX_SLEEP_TIME_MASK (0x1F << 20) > +#define EDP_PSR_SKIP_AUX_EXIT (1<<12) > +#define EDP_PSR_TP1_TP2_SEL (0<<11) > +#define EDP_PSR_TP1_TP3_SEL (1<<11) > +#define EDP_PSR_TP2_TP3_TIME_500us (0<<8) > +#define EDP_PSR_TP2_TP3_TIME_100us (1<<8) > +#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8) > +#define EDP_PSR_TP2_TP3_TIME_0us (3<<8) > +#define EDP_PSR_TP1_TIME_500us (0<<4) > +#define EDP_PSR_TP1_TIME_100us (1<<4) > +#define EDP_PSR_TP1_TIME_2500us (2<<4) > +#define EDP_PSR_TP1_TIME_0us (3<<4) > +#define EDP_PSR_IDLE_FRAME_SHIFT 0 Same thing here. > + > +#define EDP_PSR_AUX_CTL 0x64810 > +#define EDP_PSR_AUX_DATA1 0x64814 > +#define EDP_PSR_AUX_DATA2 0x64818 > +#define EDP_PSR_AUX_DATA3 0x6481c > +#define EDP_PSR_AUX_DATA4 0x64820 > +#define EDP_PSR_AUX_DATA5 0x64824 > +#define EDP_PSR_STATUS_CTL 0x64840 > +#define EDP_PSR_STATUS_MASK (7<<29) > +#define EDP_PSR_PERF_CNT 0x64844 > + > /* VGA port control */ > #define ADPA 0x61100 > #define PCH_ADPA 0xe1100 > @@ -1822,6 +1856,16 @@ > #define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4) > #define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0) > > +#define VIDEO_DIP_CTL_EDP 0x6F200 This is not needed. Take a look at HSW_VIDEO_DIP_CTL_A and the macro HSW_TVIDEO_DIP_CTL. You need to make the HSW_TVIDEO_DIP_CTL macro use cpu_transcoder instead of pipe. You can use previous patches like this one as example: http://lists.freedesktop.org/archives/intel-gfx/2012-October/020907.html > + #define VIDEOP_DIP_VSC (1<<20) See VIDEO_DIP_ENABLE_VSC_HSW. > + #define VIDEOP_DIP_GCP (1<<16) See VIDEO_DIP_ENABLE_GCP_HSW. > + #define VIDEOP_DIP_AVI (1<<12) See VIDEO_DIP_ENABLE_AVI_HSW. > + #define VIDEOP_DIP_VS (1<<8) See VIDEO_DIP_ENABLE_VS_HSW. > + #define VIDEOP_DIP_GMP (1<<4) See VIDEO_DIP_ENABLE_GMP_HSW. > + #define VIDEOP_DIP_SPD (1<<0) See VIDEO_DIP_ENABLE_SPD_HSW. > + > +#define VIDEO_DIP_VSC_DATA_EDP 0x6F320 > + Take a look at the definition of HSW_TVIDEO_DIP_CTL and similar macros. You'lll probably have to port them to use cpu_transcoder instead of pipe too. > /* Panel power sequencing */ > #define PP_STATUS 0x61200 > #define PP_ON (1 << 31) > @@ -3463,6 +3507,9 @@ > #define HSW_FUSE_STRAP 0x42014 > #define HSW_CDCLK_LIMIT (1 << 24) > > +#define CDCLK_FREQ 0x46200 > +#define CDCLK_FREQ_MASK 0x3ff Last time I checked, these registers should not be used. Please see intel_ddi_get_cdclk_freq() from intel_ddi.c. > + > /* PCH */ > > /* south display engine interrupt: IBX */ > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Paulo Zanoni
