On Fri, Jan 11, 2013 at 05:57:51PM -0200, Rodrigo Vivi wrote:
> From: Shobhit Kumar <shobhit.kumar at intel.com>
>
> Signed-off-by: Sateesh Kavuri <sateesh.kavuri at intel.com>
>
> v2: Modified and corrected the structures to be more in line for
> kernel coding guidelines and rebased the code on Paulo's DP patchset
>
> Signed-off-by: Shobhit Kumar <shobhit.kumar at intel.com>
>
> v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE
>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
DP spec stuff should be put into the drm core imo, i.e. into
include/drm/drm_dp_helper.h Since all bitfields are u8 we also have no
problems with endianess for this.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_drv.h | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 116580b..9799fe9 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -371,10 +371,38 @@ struct intel_dp {
> int backlight_on_delay;
> int backlight_off_delay;
> struct delayed_work panel_vdd_work;
> + uint8_t psr_setup;
> bool want_panel_vdd;
> struct intel_connector *attached_connector;
> };
>
> +/* SDP header as per eDP 1.3 spec, section 3.6 */
> +struct edp_sdp_header {
> + u8 id;
> + u8 type;
> + u8 revision : 5; /* Bits 0:4 */
> + u8 rsvd1 : 3; /* Bits 5:7 */
> + u8 valid_payload_bytes : 5; /* Bits 0:4 */
> + u8 rsvd2 : 3; /* Bits 5:7 */
> +} __attribute__((packed));
> +
> +/* SDP VSC header as per eDP 1.3 spec, section 3.6 */
> +struct edp_vsc_psr {
> + struct edp_sdp_header sdp_header;
> + u8 unused;
> + u8 psr_state : 1; /* Bit 0 */
> + u8 update_rfb : 1; /* Bit 1 */
> + u8 valid_crc : 1; /* Bit 2 */
> + u8 reserved1 : 5; /* Bits 3:7 */
> + u8 crc_r_lower;
> + u8 crc_r_higher;
> + u8 crc_g_lower;
> + u8 crc_g_higher;
> + u8 crc_b_lower;
> + u8 crc_b_higher;
> + u8 reserved2[24];
> +} __attribute__((packed));
> +
> struct intel_digital_port {
> struct intel_encoder base;
> enum port port;
> --
> 1.7.11.7
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
