For these objects there isn't enough backing storage even for a single
linear pixel line, so asking tiling for them is clearly a programming error.
i915_gem_get_tile_row_size() will be used by a later patch, so export it.
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 4 ++++
drivers/gpu/drm/i915/i915_gem.c | 6 ++++++
drivers/gpu/drm/i915/i915_gem_tiling.c | 3 +++
3 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c863b0f..e67332f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1570,6 +1570,10 @@ i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
uint32_t
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
int tiling_mode, bool fenced);
+
+size_t
+i915_gem_get_tile_row_size(struct drm_device *dev, int tiling_mode, int stride);
+
int i915_gem_get_tile_width(struct drm_device *dev, int tiling_mode);
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index d029e9e..e51a4cd 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1447,6 +1447,12 @@ i915_gem_get_tile_width(struct drm_device *dev, int tiling_mode)
return 512;
}
+size_t
+i915_gem_get_tile_row_size(struct drm_device *dev, int tiling_mode, int stride)
+{
+ return stride / i915_gem_get_tile_width(dev, tiling_mode) * PAGE_SIZE;
+}
+
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index e2f2a71..1a03e41 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -229,6 +229,9 @@ i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
}
}
+ if (size < i915_gem_get_tile_row_size(dev, tiling_mode, stride))
+ return false;
+
tile_width = i915_gem_get_tile_width(dev, tiling_mode);
/* 965+ just needs multiples of tile width */
--
1.7.10.4
