At the moment it's possible for user space to allocate a tiled buffer
with a size not aligned to its tile row size and corrupt a buffer that
follows this in the gtt space. More details on this in the last patch.
I'll also send an i-g-t test case for this.
Tested on Gen5,6.
Imre Deak (5):
drm/i915: merge get_gtt_alignment/get_unfenced_gtt_alignment()
drm/i915: merge {i965,sandybridge}_write_fence_reg()
drm/i915: use gtt_get_size() instead of open coding it
drm/i915: factor out i915_gem_get_tile_width()
drm/i915: fix gtt space allocated for tiled objects
drivers/gpu/drm/i915/i915_drv.h | 12 ++-
drivers/gpu/drm/i915/i915_gem.c | 144 +++++++++++++++-----------------
drivers/gpu/drm/i915/i915_gem_tiling.c | 34 +++-----
3 files changed, 89 insertions(+), 101 deletions(-)
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1.7.9.5
