Some flips could be missed when FBC + PSR link off is enabled.
Spec states that SKL, BXT, KBL and CNL needs it but probably all
other GEN9 platforms also needs it. As the power drawback would be
mininal even if not needed.
BSpec: 21664
Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index a0569fdfeb16..38167e983f1b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -845,6 +845,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
intel_de_write(dev_priv, reg, chicken);
}
+ /* WA 1110: GEN9 and GEN10 */
+ if (IS_GEN(dev_priv, 9) || IS_GEN(dev_priv, 10)) {
+ i915_reg_t reg = CHICKEN_TRANS(cpu_transcoder);
+ u32 chicken = intel_de_read(dev_priv, reg);
+
+ chicken |= UNMASK_VBLANK_PSR_LINK_OFF;
+ intel_de_write(dev_priv, reg, chicken);
+ }
+
/*
* Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also
* mask LPSP to avoid dependency on other drivers that might block
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 17484345cb80..abb37437ff5d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7821,6 +7821,7 @@ enum {
[TRANSCODER_B] = _CHICKEN_TRANS_B, \
[TRANSCODER_C] = _CHICKEN_TRANS_C, \
[TRANSCODER_D] = _CHICKEN_TRANS_D))
+#define UNMASK_VBLANK_PSR_LINK_OFF (1 << 30)
#define HSW_FRAME_START_DELAY_MASK (3 << 27)
#define HSW_FRAME_START_DELAY(x) ((x) << 27) /* 0-3 */
#define VSC_DATA_SEL_SOFTWARE_CONTROL (1 << 25) /* GLK and CNL+ */
--
2.26.0
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