On Thu, 27 Sep 2012 19:13:01 +0530
Vijay Purushothaman <vijay.a.purushothaman at intel.com> wrote:
> Set hrawclk to 200 MHz and aux divider clock to 100 MHz for Valleyview.
> This enables the aux transactions in Valleyview.
>
> Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman at intel.com>
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index a69d9a2..de8092a 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -285,6 +285,10 @@ intel_hrawclk(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t clkcfg;
>
> + /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
> + if (IS_VALLEYVIEW(dev))
> + return 200;
> +
> clkcfg = I915_READ(CLKCFG);
> switch (clkcfg & CLKCFG_FSB_MASK) {
> case CLKCFG_FSB_400:
> @@ -365,7 +369,9 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> * clock divider.
> */
> if (is_cpu_edp(intel_dp)) {
> - if (IS_GEN6(dev) || IS_GEN7(dev))
> + if (IS_VALLEYVIEW(dev))
> + aux_clock_divider = 100;
> + else if (IS_GEN6(dev) || IS_GEN7(dev))
> aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> else
> aux_clock_divider = 225; /* eDP input clock at 450Mhz */
Acked-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Hopefully I'll get a chance to test later today. I'm tracking down a
regression in the gmbus based edid probing in the -next based tree I'm
using...
--
Jesse Barnes, Intel Open Source Technology Center
