On 9/26/2012 8:10 PM, Daniel Vetter wrote:
> On Wed, Sep 26, 2012 at 07:07:38PM +0530, Vijay Purushothaman wrote:
>> From: "Bhat, Gajanan" <gajanan.bhat at intel.com>
>>
>> Clened up DPLL calculations for Valleyview. Moved DPLL register and DPIO
>> programming to vlv_update_pll function. With all the changes multi
>> display (clone, extended desktop) should work for VLV.
>>
>> Signed-off-by: Gajanan Bhat <gajanan.bhat at intel.com>
>
> I guess this patch will look much better once we don't disable the
> vlv_update_pll function in between (and apply my other suggestion to move
> i9xx_update_pll_divisors into the !vlv pll functions).
> -Daniel
I've merged patch 5 and 9 and took care of your suggestions.
Thanks,
Vijay
>
>> ---
>> drivers/gpu/drm/i915/i915_reg.h | 8 +--
>> drivers/gpu/drm/i915/intel_display.c | 105 ++++++++++++++++++----------------
>> 2 files changed, 58 insertions(+), 55 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index d4ed30e..71aa0a7 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -385,12 +385,8 @@
>>
>> #define DPIO_FASTCLK_DISABLE 0x8100
>>
>> -#define _DPIO_DATA_LANE0 0x0220
>> -#define _DPIO_DATA_LANE1 0x0420
>> -#define _DPIO_DATA_LANE2 0x2620
>> -#define _DPIO_DATA_LANE3 0x2820
>> -#define DPIO_DATA_LANE_A(pipe) _PIPE(pipe, _DPIO_DATA_LANE0, _DPIO_DATA_LANE2)
>> -#define DPIO_DATA_LANE_B(pipe) _PIPE(pipe, _DPIO_DATA_LANE1, _DPIO_DATA_LANE3)
>> +#define DPIO_DATA_CHANNEL1 0x8220
>> +#define DPIO_DATA_CHANNEL2 0x8420
>>
>> /*
>> * Fence registers
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 647e311..e933031 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -4018,10 +4018,10 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
>> }
>>
>> static void vlv_update_pll(struct drm_crtc *crtc,
>> - struct drm_display_mode *mode,
>> - struct drm_display_mode *adjusted_mode,
>> - intel_clock_t *clock, intel_clock_t *reduced_clock,
>> - int refclk, int num_connectors)
>> + struct drm_display_mode *mode,
>> + struct drm_display_mode *adjusted_mode,
>> + intel_clock_t *clock, intel_clock_t *reduced_clock,
>> + int num_connectors)
>> {
>> struct drm_device *dev = crtc->dev;
>> struct drm_i915_private *dev_priv = dev->dev_private;
>> @@ -4029,9 +4029,19 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>> int pipe = intel_crtc->pipe;
>> u32 dpll, mdiv, pdiv;
>> u32 bestn, bestm1, bestm2, bestp1, bestp2;
>> - bool is_hdmi;
>> + bool is_sdvo;
>> + u32 temp;
>>
>> - is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>> + is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
>> + intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>> +
>> + dpll = DPLL_VGA_MODE_DIS;
>> + dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
>> + dpll |= DPLL_REFA_CLK_ENABLE_VLV;
>> + dpll |= DPLL_INTEGRATED_CLOCK_VLV;
>> +
>> + I915_WRITE(DPLL(pipe), dpll);
>> + POSTING_READ(DPLL(pipe));
>>
>> bestn = clock->n;
>> bestm1 = clock->m1;
>> @@ -4039,12 +4049,10 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>> bestp1 = clock->p1;
>> bestp2 = clock->p2;
>>
>> - /* Enable DPIO clock input */
>> - dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
>> - DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
>> - I915_WRITE(DPLL(pipe), dpll);
>> - POSTING_READ(DPLL(pipe));
>> -
>> + /*
>> + * In Valleyview PLL and program lane counter registes are exposed
>> + * through DPIO interface
>> + */
>> mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
>> mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
>> mdiv |= ((bestn << DPIO_N_SHIFT));
>> @@ -4069,21 +4077,47 @@ static void vlv_update_pll(struct drm_crtc *crtc,
>> if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
>> DRM_ERROR("DPLL %d failed to lock\n", pipe);
>>
>> - if (is_hdmi) {
>> - u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>> + intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>> +
>> + if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>> + intel_dp_set_m_n(crtc, mode, adjusted_mode);
>> +
>> + I915_WRITE(DPLL(pipe), dpll);
>> +
>> + /* Wait for the clocks to stabilize. */
>> + POSTING_READ(DPLL(pipe));
>> + udelay(150);
>>
>> + temp = 0;
>> + if (is_sdvo) {
>> + temp = intel_mode_get_pixel_multiplier(adjusted_mode);
>> if (temp > 1)
>> temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
>> else
>> temp = 0;
>> -
>> - I915_WRITE(DPLL_MD(pipe), temp);
>> - POSTING_READ(DPLL_MD(pipe));
>> }
>> + I915_WRITE(DPLL_MD(pipe), temp);
>> + POSTING_READ(DPLL_MD(pipe));
>>
>> - intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
>> + /* Now program lane control registers */
>> + if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
>> + || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
>> + {
>> + temp = 0x1000C4;
>> + if(pipe == 1)
>> + temp |= (1 << 21);
>> + intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
>> + }
>> + if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
>> + {
>> + temp = 0x1000C4;
>> + if(pipe == 1)
>> + temp |= (1 << 21);
>> + intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
>> + }
>> }
>>
>> +
>> static void i9xx_update_pll(struct drm_crtc *crtc,
>> struct drm_display_mode *mode,
>> struct drm_display_mode *adjusted_mode,
>> @@ -4096,10 +4130,8 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>> int pipe = intel_crtc->pipe;
>> u32 dpll;
>> bool is_sdvo;
>> -
>> is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
>> intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
>> -
>> dpll = DPLL_VGA_MODE_DIS;
>>
>> if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
>> @@ -4117,12 +4149,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>> if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
>> dpll |= DPLL_DVO_HIGH_SPEED;
>>
>> - if (IS_VALLEYVIEW(dev)) {
>> - dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
>> - dpll |= DPLL_REFA_CLK_ENABLE_VLV;
>> - dpll |= DPLL_INTEGRATED_CLOCK_VLV;
>> - }
>> -
>> /* compute bitmask from p1 value */
>> if (IS_PINEVIEW(dev))
>> dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
>> @@ -4164,18 +4190,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>> I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
>> POSTING_READ(DPLL(pipe));
>>
>> - /*
>> - * In Valleyview PLL and program lane counter registes are exposed
>> - * through DPIO interface
>> - */
>> - if (IS_VALLEYVIEW(dev)) {
>> - int refclk;
>> - refclk = i9xx_get_refclk(crtc, num_connectors);
>> - vlv_update_pll(crtc, mode, adjusted_mode, clock, NULL, refclk,
>> - num_connectors);
>> - }
>> - udelay(150);
>> -
>> /* The LVDS pin pair needs to be on before the DPLLs are enabled.
>> * This is an exception to the general rule that mode_set doesn't turn
>> * things on.
>> @@ -4192,17 +4206,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
>> POSTING_READ(DPLL(pipe));
>> udelay(150);
>>
>> - /* Now program lane control registers for Valleyview */
>> - if (IS_VALLEYVIEW(dev)) {
>> - u32 temp = 0;
>> - temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_A(pipe));
>> - temp |= (1 << 20);
>> - intel_dpio_write(dev_priv, DPIO_DATA_LANE_A(pipe), temp);
>> - temp = intel_dpio_read(dev_priv, DPIO_DATA_LANE_B(pipe));
>> - temp |= (1 << 20);
>> - intel_dpio_write(dev_priv, DPIO_DATA_LANE_B(pipe), temp);
>> - }
>> -
>> if (INTEL_INFO(dev)->gen >= 4) {
>> u32 temp = 0;
>> if (is_sdvo) {
>> @@ -4365,6 +4368,10 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
>>
>> if (IS_GEN2(dev))
>> i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
>> + else if (IS_VALLEYVIEW(dev))
>> + vlv_update_pll(crtc, mode, adjusted_mode, &clock,
>> + has_reduced_clock ? &reduced_clock : NULL,
>> + num_connectors);
>> else
>> i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
>> has_reduced_clock ? &reduced_clock : NULL,
>> --
>> 1.7.9.5
>>
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>
