From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> On pre-ivb the CS timestamp register is only present on RCS (despite what snb bspec claims). Let's test it. Also on ctg/elk/ilk the usable part of the timestamp is the UDW so let's read that instead of the LDW. On ctg/elk the 10 msbs of the LDW do actually work, but we configure cs_timestamp_frequency_hz as if they didn't so that we can treat ctg/elk the same as ilk. TODO: figure out why the results we get aren't reliable. On some iterations we can get totally wrong (though consistent) values, on other iterations the values are correct. And somehow changing the offsets into the hwsp also seems to affect the behaviour. Manually reading the register always seems fine, so feels like the problem has something to do with the store rather than the actual register read. Cc: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx> Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 27 +++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c index f88e445a1cae..f92542e6b5b8 100644 --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c @@ -52,7 +52,10 @@ static int write_timestamp(struct i915_request *rq, int slot) if (INTEL_GEN(rq->i915) >= 8) cmd++; *cs++ = cmd; - *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base)); + if (IS_GEN(rq->i915, 5) || IS_G4X(rq->i915)) + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP_UDW(rq->engine->mmio_base)); + else + *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(rq->engine->mmio_base)); *cs++ = i915_request_timeline(rq)->hwsp_offset + slot * sizeof(u32); *cs++ = 0; @@ -122,7 +125,8 @@ static int perf_mi_bb_start(void *arg) enum intel_engine_id id; int err = 0; - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */ + /* Do we have any CS_TIMESTAMP? */ + if (INTEL_GEN(gt->i915) < 4) return 0; perf_begin(gt); @@ -132,6 +136,14 @@ static int perf_mi_bb_start(void *arg) u32 cycles[COUNT]; int i; + /* + * Do we have CS_TIMESTAMP for this engine? + * Despite what bspec says SNB does not have this + * for other engines. + */ + if (INTEL_GEN(gt->i915) < 7 && id != RCS0) + continue; + intel_engine_pm_get(engine); batch = create_empty_batch(ce); @@ -246,7 +258,8 @@ static int perf_mi_noop(void *arg) enum intel_engine_id id; int err = 0; - if (INTEL_GEN(gt->i915) < 7) /* for per-engine CS_TIMESTAMP */ + /* Do we have any CS_TIMESTAMP? */ + if (INTEL_GEN(gt->i915) < 4) return 0; perf_begin(gt); @@ -256,6 +269,14 @@ static int perf_mi_noop(void *arg) u32 cycles[COUNT]; int i; + /* + * Do we have CS_TIMESTAMP for this engine? + * Despite what bspec says SNB does not have this + * for other engines. + */ + if (INTEL_GEN(gt->i915) < 7 && id != RCS0) + continue; + intel_engine_pm_get(engine); base = create_empty_batch(ce); -- 2.24.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
