From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
Despite what the spec says the TIMESTAMP register seems to tick
once every hrawclk (confirmed on i965gm and g35).
Cc: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/intel_device_info.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index b756e8fb7682..be88eb41035a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -748,8 +748,10 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
* "The value in this register increments once every 16
* hclks." (through the “Clocking Configuration”
* (“CLKCFG”) MCHBAR register)
+ *
+ * Testing on actual hardware has shown there is no /16.
*/
- return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
+ return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000;
} else if (IS_G4X(dev_priv)) {
/*
* 63:20 increments every 1/4 ns
--
2.24.1
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