In order to keep our cached values in sync with the hardware, we need a posting read here. CC: Chris Wilson <chris at chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben at bwidawsk.net> --- drivers/gpu/drm/i915/intel_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 36c6409..4e86037 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val) */ I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); + POSTING_READ(GEN6_RPNSWREQ); + dev_priv->rps.cur_delay = val; trace_intel_gpu_freq_change(val * 50); -- 1.7.12
