Hi
2012/10/29 Daniel Vetter <daniel.vetter at ffwll.ch>:
> They are all written for a specific north disaplay->pch combination.
> So stop pretending otherwise.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 14 +++++---------
> 1 file changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3b62999..129059b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2409,11 +2409,9 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
> udelay(150);
>
> /* Ironlake workaround, enable clock pointer after FDI enable*/
> - if (HAS_PCH_IBX(dev)) {
> - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
> - I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
> - FDI_RX_PHASE_SYNC_POINTER_EN);
> - }
> + I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
> + I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
> + FDI_RX_PHASE_SYNC_POINTER_EN);
>
> reg = FDI_RX_IIR(pipe);
> for (tries = 0; tries < 5; tries++) {
> @@ -2519,8 +2517,7 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
> POSTING_READ(reg);
> udelay(150);
>
> - if (HAS_PCH_CPT(dev))
> - cpt_phase_pointer_enable(dev, pipe);
> + cpt_phase_pointer_enable(dev, pipe);
>
> for (i = 0; i < 4; i++) {
> reg = FDI_TX_CTL(pipe);
> @@ -2654,8 +2651,7 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
> POSTING_READ(reg);
> udelay(150);
>
> - if (HAS_PCH_CPT(dev))
> - cpt_phase_pointer_enable(dev, pipe);
> + cpt_phase_pointer_enable(dev, pipe);
>
> for (i = 0; i < 4; i++) {
> reg = FDI_TX_CTL(pipe);
> --
> 1.7.11.4
>
> _______________________________________________
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> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Paulo Zanoni
