On Sat, Oct 27, 2012 at 2:15 PM, Paulo Zanoni <przanoni at gmail.com> wrote: > I'm not sure what's the problem with the current code. Could you > please explain a little bit more? After a brief look at > intel_enable_pch_pll and intel_disable_pch_pll it seems our code does > try to check the pll refcount and behave correctly. I'm not an expert > of the ILK PCH pll sharing code, so I may be missing something. Indeed, the comment is at the wrong place, but I _did_ remember the code correctly: In get_pch_pll we unconditionally rewrite (and in doing so, disable) the pch_pll and reset pll->on, even when the pll is currently on and used already. We can't just fix this, since the lvds enable code _requires_ that the pll is off (otherwise the ldvs pin pair enabling will fail). So it's not that easy to fix. I'll update the comment. Thanks, Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
