Hi
2012/10/26 Daniel Vetter <daniel.vetter at ffwll.ch>:
> My machine here has the correct ones already, but better safe
> than sorry. IBX has different settings for that register, and
> on IBX the device defaults match the recommended values. Hence
> I did not add the respective writes for IBX.
>
> LPT needs the same settings, but that has been done already
>
> commit 4acf518626cdad5bbf7aac9869bd4accbbfb4ad3
> Author: Eugeni Dodonov <eugeni.dodonov at intel.com>
> Date: Wed Jul 4 20:15:16 2012 -0300
>
> drm/i915: program FDI_RX TP and FDI delays
>
> Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 6cc9cb9..b19e3bb 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2460,6 +2460,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
> temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
> I915_WRITE(reg, temp | FDI_TX_ENABLE);
>
> + I915_WRITE(FDI_RX_MISC(pipe),
> + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> +
On my local HSW branch I changed this code on the LPT path to first
I915_READ the register, then mask and change the values we want, then
write again. This way we preserve the values set for the other bits. I
did this because I discovered I needed to change the other bits in
other places for some workarounds. So maybe you could do this for
CPT/PPT too?
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> if (HAS_PCH_CPT(dev)) {
> @@ -2592,6 +2595,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
> temp |= FDI_COMPOSITE_SYNC;
> I915_WRITE(reg, temp | FDI_TX_ENABLE);
>
> + I915_WRITE(FDI_RX_MISC(pipe),
> + FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
> +
> reg = FDI_RX_CTL(pipe);
> temp = I915_READ(reg);
> temp &= ~FDI_LINK_TRAIN_AUTO;
> --
> 1.7.11.4
>
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--
Paulo Zanoni
