On Tue, 23 Oct 2012 12:57:24 -0700 Ben Widawsky <ben at bwidawsk.net> wrote: > On Tue, 23 Oct 2012 16:58:50 +0200 > Daniel Vetter <daniel at ffwll.ch> wrote: > > > On Tue, Oct 23, 2012 at 4:57 PM, Ben Widawsky <ben at bwidawsk.net> wrote: > > > Actually, after we introduce the FLSH_CNTL patch from Jesse/me later in the > > > series, I think we just want a POSTING_READ on that register. It is > > > technically "required" by our desire to some day WC the registers, and > > > should synchronize everything else for us. > > > > > > After a quick read of memory_barriers.txt (again), I think mmiowb is > > > actually what we might want in addition to the POSTING_READ I'd add. > > > > Imo we have special rules for the igd, since clearly not all registers > > in our 4mb mmio window are equal. So I'd prefer the keep the readback > > of the last pte write (to ensure those are flushed out) and maybe also > > add a readback of the gfx_flsh_cntl reg (like I've seen in some > > internal vlv tree). Just to be paranoid. > > -Daniel > > What's your definition of flush? I think we just need one read to > satisfy the device I/O flush, and I think the write to the regsiter > should satisy the TLB flush. That leads me to the conclusion that just > the POSTING_READ of the FLSH_CNTL register is sufficient. > > If you want me to do both, I have no problem with that either, and I'll > just update the comment to say that we believe it is unnecessary. > > I don't really care either way. Yeah we just need one or the other, not both. Technically the UC write of the flush control reg should flush the WC buffer, then a posting read of the flush control reg should make sure it gets to device 2 before the read returns. -- Jesse Barnes, Intel Open Source Technology Center
