On Mon, 22 Oct 2012 18:34:06 -0700
Ben Widawsky <ben at bwidawsk.net> wrote:
> The mid-level cache or as it's more commonly referred to now as L3, is
> not setup this way on HSW.
>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index 47e427e..5751ad2 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -218,7 +218,11 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
>
> switch (cache_level) {
> case I915_CACHE_LLC_MLC:
> - pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
> + /* Haswell doesn't set L3 this way */
> + if (IS_HASWELL(obj->base.dev))
> + pte_flags |= GEN6_PTE_CACHE_LLC;
> + else
> + pte_flags |= GEN6_PTE_CACHE_LLC_MLC;
> break;
> case I915_CACHE_LLC:
> pte_flags |= GEN6_PTE_CACHE_LLC;
> @@ -253,12 +257,12 @@ static unsigned int cache_level_to_agp_type(struct drm_device *dev,
> {
> switch (cache_level) {
> case I915_CACHE_LLC_MLC:
> - if (INTEL_INFO(dev)->gen >= 6)
> - return AGP_USER_CACHED_MEMORY_LLC_MLC;
> /* Older chipsets do not have this extra level of CPU
> * cacheing, so fallthrough and request the PTE simply
> * as cached.
> */
> + if (INTEL_INFO(dev)->gen >= 6 && !IS_HASWELL(dev))
> + return AGP_USER_CACHED_MEMORY_LLC_MLC;
> case I915_CACHE_LLC:
> return AGP_USER_CACHED_MEMORY;
> default:
We might want a .has_mlc or something here at some point, but that
doesn't have to happen here.
Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
