On Sat, 20 Oct 2012 20:57:43 +0200
Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> We need this when the bios forgets even to set that bit up. Most seem
> to do that, even when they don't set up anything else in the panel
> power sequencer.
>
> Note that on IBX the rawclk is variable according to Bspec, but
> everyone is using 125MHz. The rawclk is fixed to 125MHz on CPT, but
> luckily we still have the same register available. On hsw, different
> variants have different clocks, hence we need to check the register.
>
> Since other pieces are driven by the rawclock, too, keep the little
> helper in a central place.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++
> drivers/gpu/drm/i915/intel_dp.c | 8 ++++++--
> drivers/gpu/drm/i915/intel_drv.h | 2 ++
> 3 files changed, 18 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 9c17a0a7..7fb032f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -80,6 +80,16 @@ struct intel_limit {
> /* FDI */
> #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
>
> +int
> +intel_pch_rawclk(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> +
> + WARN_ON(!HAS_PCH_SPLIT(dev));
> +
> + return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
> +}
> +
> static bool
> intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
> int target, int refclk, intel_clock_t *match_clock,
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 49846c0..b35d5bd 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -2749,8 +2749,12 @@ intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
> (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
> pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
> (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
> - pp_div = (pp_div & PP_REFERENCE_DIVIDER_MASK) |
> - (DIV_ROUND_UP(final.t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT);
> + /* Compute the divisor for the pp clock, simply match the Bspec
> + * formula. */
> + pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
> + << PP_REFERENCE_DIVIDER_SHIFT;
> + pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
> + << PANEL_POWER_CYCLE_DELAY_SHIFT);
>
> /* Haswell doesn't have any port selection bits for the panel
> * power sequence any more. */
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index ed75a36..39bddd7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -396,6 +396,8 @@ struct intel_fbc_work {
> int interval;
> };
>
> +int intel_pch_rawclk(struct drm_device *dev);
> +
> int intel_connector_update_modes(struct drm_connector *connector,
> struct edid *edid);
> int intel_ddc_get_modes(struct drm_connector *c, struct i2c_adapter *adapter);
Did you check that the calculation generally matched the existing value
on the machines you looked at?
Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
--
Jesse Barnes, Intel Open Source Technology Center
