From: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
The panel power sequencer can get confused if we follow a
PP_ON_DELAYS write with a PP_CONTROL power state target write.
Apparently it can latch the old PP_ON_DELAYS value instead of
the new one. Instead of mucking about with clock gating disables
until we enable the power sequencer let's just do the trivial
100us+ delay.
Signed-off-by: Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx>
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 0f496115c345..9cb2ec91039f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6876,6 +6876,17 @@ intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp,
} else {
u32 pp_ctl;
+ /*
+ * Display WA #1124: bxt,glk,cnl
+ * "WA: Wait at least 100us between programming
+ * PP_ON_DELAYS and enabling Power State Target in
+ * PP_CONTROL, or disable dpls clock gating before
+ * programming PP_ON_DELAYS and leave disabled until
+ * after enabling Power State Target in PP_CONTROL."
+ */
+ if (INTEL_GEN(dev_priv) < 11)
+ usleep_range(100, 200);
+
pp_ctl = I915_READ(regs.pp_ctrl);
pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK;
pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000));
--
2.23.0
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