Hi
2012/10/19 Damien Lespiau <damien.lespiau at gmail.com>:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> With the consolidated registers, it appears that we're setting the same
> bis several times. Let's just collect the bits we want to set and program
> it once.
>
> v2: More cleanup. Also program 0x42004 and 0x45000 for FBC on non
> mobile platforms (Paulo Zanoni)
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 37 ++++++++++++-------------------------
> 1 files changed, 12 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e8a6076..b4120c9 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3297,21 +3297,12 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
> uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> - /* Required for FBC */
> - dspclk_gate |= ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> - /* Required for CxSR */
> - dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> -
> I915_WRITE(PCH_3DCGDIS0,
> MARIUNIT_CLOCK_GATE_DISABLE |
> SVSMUNIT_CLOCK_GATE_DISABLE);
> I915_WRITE(PCH_3DCGDIS1,
> VFMUNIT_CLOCK_GATE_DISABLE);
>
> - I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
> -
> /*
> * According to the spec the following bits should be set in
> * order to enable memory self-refresh
> @@ -3322,9 +3313,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> (I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> - I915_WRITE(ILK_DSPCLK_GATE_D,
> - (I915_READ(ILK_DSPCLK_GATE_D) |
> - ILK_DPARBUNIT_CLOCK_GATE_ENABLE));
> + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
> I915_WRITE(DISP_ARB_CTL,
> (I915_READ(DISP_ARB_CTL) |
> DISP_FBC_WM_DIS));
> @@ -3339,19 +3328,17 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> * The bit 22 of 0x42004
> * The bit 7,8,9 of 0x42020.
> */
> - if (IS_IRONLAKE_M(dev)) {
> - I915_WRITE(ILK_DISPLAY_CHICKEN1,
> - I915_READ(ILK_DISPLAY_CHICKEN1) |
> - ILK_FBCQ_DIS);
> - I915_WRITE(ILK_DISPLAY_CHICKEN2,
> - I915_READ(ILK_DISPLAY_CHICKEN2) |
> - ILK_DPARB_GATE);
> - I915_WRITE(ILK_DSPCLK_GATE_D,
> - I915_READ(ILK_DSPCLK_GATE_D) |
> - ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> - ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
> - }
> + I915_WRITE(ILK_DISPLAY_CHICKEN1,
> + I915_READ(ILK_DISPLAY_CHICKEN1) |
> + ILK_FBCQ_DIS);
> + I915_WRITE(ILK_DISPLAY_CHICKEN2,
> + I915_READ(ILK_DISPLAY_CHICKEN2) |
> + ILK_DPARB_GATE);
This is not exactly what I suggested, I think those 2 regs could stay
inside the if is_mobile, just move the dspclk_gate outside (so we keep
the current behavior).
With that:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> + dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
> +
> + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> --
> 1.7.7.5
>
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--
Paulo Zanoni
