Hi
2012/10/17 Damien Lespiau <damien.lespiau at gmail.com>:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> Register 0x42020 was defined twice under the names PCH_DSPCLK_GATE_D and
> ILK_DSPCLK_GATE. This patch consolidate the 2 sets of defines in one.
>
> The transforms done are:
>
> PCH_DSPCLK_GATE_D -> ILK_DSPCLK_GATE_D
> ILK_DSPCLK_GATE -> ILK_DSPCLK_GATE_D
>
> DPARBUNIT_CLOCK_GATE_DISABLE -> ILK_DPARBUNIT_CLOCK_GATE_DISABLE
> ILK_DPARB_CLK_GATE -> ILK_DPARBUNIT_CLOCK_GATE_DISABLE
>
> DPFDUNIT_CLOCK_GATE_DISABLE -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
> ILK_DPFD_CLK_GATE -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
> ILK_CLK_FBC -> ILK_DPFDUNIT_CLOCK_GATE_DISABLE
>
> DPFCRUNIT_CLOCK_GATE_DISABLE -> ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
> ILK_DPFC_DIS1 -> ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
>
> DPFCUNIT_CLOCK_GATE_DISABLE -> ILK_DPFCUNIT_CLOCK_GATE_DISABLE
> ILK_DPFC_DIS2 -> ILK_DPFCUNIT_CLOCK_GATE_DISABLE
>
> We have a VHRUNIT_CLOCK_GATE_DISABLE define for the pre-ILK DSPCLK_GATE_D.
> Even if the same bit is used in ILK_DSPCLK_GATE_D, other bits in the
> register change, so I went with re-defining it, well more precisely rename
> IVB_VRHUNIT_CLK_GATE, which is not specific to IVB+. So:
>
> IVB_VRHUNIT_CLK_GATE -> ILK_VHRUNIT_CLOCK_GATE_DISABLE
> VHRUNIT_CLOCK_GATE_DISABLE -> ILK_VHRUNIT_CLOCK_GATE_DISABLE (ILK+ code)
>
> This commit is only a renaming commit, further commits will clean up the
> logic.
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 22 +++++-----------
> drivers/gpu/drm/i915/intel_pm.c | 52 +++++++++++++++++++-------------------
> 2 files changed, 33 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8200c31..ac09d66 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3245,12 +3245,6 @@
> #define DISPLAY_PORT_PLL_BIOS_1 0x46010
> #define DISPLAY_PORT_PLL_BIOS_2 0x46014
>
> -#define PCH_DSPCLK_GATE_D 0x42020
> -# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
> -# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
> -# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
> -# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
> -
> #define PCH_3DCGDIS0 0x46020
> # define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
> # define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
> @@ -3422,15 +3416,13 @@
> #define ILK_HDCP_DISABLE (1<<25)
> #define ILK_eDP_A_DISABLE (1<<24)
> #define ILK_DESKTOP (1<<23)
> -#define ILK_DSPCLK_GATE 0x42020
> -#define IVB_VRHUNIT_CLK_GATE (1<<28)
> -#define ILK_DPARB_CLK_GATE (1<<5)
> -#define ILK_DPFD_CLK_GATE (1<<7)
> -
> -/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
> -#define ILK_CLK_FBC (1<<7)
> -#define ILK_DPFC_DIS1 (1<<8)
> -#define ILK_DPFC_DIS2 (1<<9)
> +
> +#define ILK_DSPCLK_GATE_D 0x42020
> +#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
> +#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
> +#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
> +#define ILK_DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
> +#define ILK_DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
Setting bits 7 and 5 to "1" actually means "enable", even though the
bit name is "dxxxunit clock gating disable". So my suggestion would
be:
+#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
+#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
The other bits are fine, since setting them to 1 actually means "disable".
With that fixed:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> #define IVB_CHICKEN3 0x4200c
> # define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 07da990..76e10c0 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3301,14 +3301,14 @@ void intel_enable_gt_powersave(struct drm_device *dev)
> static void ironlake_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> + uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> /* Required for FBC */
> - dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
> - DPFCRUNIT_CLOCK_GATE_DISABLE |
> - DPFDUNIT_CLOCK_GATE_DISABLE;
> + dspclk_gate |= ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_DISABLE;
> /* Required for CxSR */
> - dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
> + dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_DISABLE;
>
> I915_WRITE(PCH_3DCGDIS0,
> MARIUNIT_CLOCK_GATE_DISABLE |
> @@ -3316,7 +3316,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> I915_WRITE(PCH_3DCGDIS1,
> VFMUNIT_CLOCK_GATE_DISABLE);
>
> - I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
> + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> /*
> * According to the spec the following bits should be set in
> @@ -3328,9 +3328,9 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> (I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_DPARB_GATE | ILK_VSDPFD_FULL));
> - I915_WRITE(ILK_DSPCLK_GATE,
> - (I915_READ(ILK_DSPCLK_GATE) |
> - ILK_DPARB_CLK_GATE));
> + I915_WRITE(ILK_DSPCLK_GATE_D,
> + (I915_READ(ILK_DSPCLK_GATE_D) |
> + ILK_DPARBUNIT_CLOCK_GATE_DISABLE));
> I915_WRITE(DISP_ARB_CTL,
> (I915_READ(DISP_ARB_CTL) |
> DISP_FBC_WM_DIS));
> @@ -3352,11 +3352,11 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_DPARB_GATE);
> - I915_WRITE(ILK_DSPCLK_GATE,
> - I915_READ(ILK_DSPCLK_GATE) |
> - ILK_DPFC_DIS1 |
> - ILK_DPFC_DIS2 |
> - ILK_CLK_FBC);
> + I915_WRITE(ILK_DSPCLK_GATE_D,
> + I915_READ(ILK_DSPCLK_GATE_D) |
> + ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_DISABLE);
> }
>
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> @@ -3371,9 +3371,9 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
> - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> + uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> - I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
> + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> @@ -3428,10 +3428,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> I915_WRITE(ILK_DISPLAY_CHICKEN2,
> I915_READ(ILK_DISPLAY_CHICKEN2) |
> ILK_DPARB_GATE | ILK_VSDPFD_FULL);
> - I915_WRITE(ILK_DSPCLK_GATE,
> - I915_READ(ILK_DSPCLK_GATE) |
> - ILK_DPARB_CLK_GATE |
> - ILK_DPFD_CLK_GATE);
> + I915_WRITE(ILK_DSPCLK_GATE_D,
> + I915_READ(ILK_DSPCLK_GATE_D) |
> + ILK_DPARBUNIT_CLOCK_GATE_DISABLE |
> + ILK_DPFDUNIT_CLOCK_GATE_DISABLE);
>
> I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
> GEN6_MBCTL_ENABLE_BOOT_FETCH);
> @@ -3513,16 +3513,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
> - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> + uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
> uint32_t snpcr;
>
> - I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
> + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> I915_WRITE(WM3_LP_ILK, 0);
> I915_WRITE(WM2_LP_ILK, 0);
> I915_WRITE(WM1_LP_ILK, 0);
>
> - I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
> + I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>
> /* WaDisableEarlyCull */
> I915_WRITE(_3D_CHICKEN3,
> @@ -3595,15 +3595,15 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> int pipe;
> - uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
> + uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
>
> - I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
> + I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
>
> I915_WRITE(WM3_LP_ILK, 0);
> I915_WRITE(WM2_LP_ILK, 0);
> I915_WRITE(WM1_LP_ILK, 0);
>
> - I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
> + I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
>
> /* WaDisableEarlyCull */
> I915_WRITE(_3D_CHICKEN3,
> --
> 1.7.7.5
>
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--
Paulo Zanoni
