Putting down the AUX power domain reference count in edp vdd off async sequence takes too much of time (relative to panel power cycle delay) therefore it make sense to expose the panel power cycle delay to i915_panel_timings along with other delays. It can be use by DC state IGT to wait for strict power cycle delay in order to check for various DC state counters. Cc: Imre Deak <imre.deak@xxxxxxxxx> Signed-off-by: Anshuman Gupta <anshuman.gupta@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index cab632791f73..c075cc2b7bb5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4436,6 +4436,8 @@ static int i915_panel_show(struct seq_file *m, void *data) intel_dp->panel_power_up_delay); seq_printf(m, "Panel power down delay: %d\n", intel_dp->panel_power_down_delay); + seq_printf(m, "Panel power cycle delay: %d\n", + intel_dp->panel_power_cycle_delay); seq_printf(m, "Backlight on delay: %d\n", intel_dp->backlight_on_delay); seq_printf(m, "Backlight off delay: %d\n", -- 2.24.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
