On Sun, Oct 14, 2012 at 04:33:11PM +0200, Egbert Eich wrote: > The DPLL multipiler is set up in intel_display.c:i9xx_update_pll() > called from i9xx_crtc_mode_set(). > There the DPLL multiplier is adjusted so that the SDVO gets a sufficient > bus clock. > When cloning a CRTC between an SDVO driven encoder and the standard > DAC the DAC setup code reseted the multiplier value to 1 thus undoing > the correct setup. There is no need to touch the multiplier in the DAC > setup code: the correct value (i.e. 1 in case no SDVO encoder is used) > is set by i9xx_update_pll() already. > A comment at the code suggested that this code is a left over from the > days when there was no setup for clone modes. > > Signed-off-by: Egbert Eich <eich at suse.de> Picked up for -fixes, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
