On Fri, Oct 05, 2012 at 10:40:35AM -0300, Paulo Zanoni wrote: > 2012/10/5 Damien Lespiau <damien.lespiau at gmail.com>: > > From: Damien Lespiau <damien.lespiau at intel.com> > > > > There's is another register (a read only, so no harm done) at 0x42020 on > > Haswell GPUs. Let's just remove the write from the copy&paste that > > introduced haswell_init_clock_gating(). > > > > A note for the interested reader, it does seem we have a duplication of > > the 0x42020 register definition, hence the removal of 2 writes. That > > duplication could be the object of a later patch. > > > > Signed-off-by: Damien Lespiau <damien.lespiau at intel.com> > > Cc: Paulo Zanoni <paulo.r.zanoni at intel.com> > > Nice catch! > > As you pointed, it seems that we're applying the same workaround twice > in some functions. You fixed the problem in haswell_init_clock_gating > by just removing both register writes, but could you also write a new > patch to fix ivybridge_init_clock_gating and > valleyview_init_clock_gating to not apply the same workaround twice? > Maybe just remove the ILK_DSPCLK_GATE definitions and just use > PCH_DSPCLK_GATE_D everywhere, removing duplicated code? Then we'd also > have to check ironlake_init_clock_gating and gen6_init_clock_gating... > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com> > Tested-by: Paulo Zanoni <paulo.r.zanoni at intel.com> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
