On Mon, 14 Oct 2019, Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx> wrote:
> Configure the transcoder to operate in TE GATE command mode
> and take TE events from GPIO.
> Also disable the periodic command mode, that GOP would have
> programmed.
>
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 32 ++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 6e398c33a524..8e6c09a1db78 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -704,6 +704,10 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> tmp |= VIDEO_MODE_SYNC_PULSE;
> break;
> }
> + } else {
> + tmp &= ~OP_MODE_MASK;
> + tmp |= CMD_MODE_TE_GATE;
> + tmp |= TE_SOURCE_GPIO;
> }
>
> I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> @@ -953,6 +957,22 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
> }
> }
>
> +static void gen11_dsi_config_util_pin(struct intel_encoder *encoder)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> + u32 tmp;
> +
> + /* used only as TE i/p for DSI0 for dual link TE is from slave DSI1 */
> + if (is_vid_mode(intel_dsi) || (intel_dsi->dual_link))
> + return;
Full disclosure: I didn't check the spec on this.
But... where does the TE come for the slave DSI1 then? The comment seems
confusing.
Nitpick, intel_dsi->dual_link does not need parenthesis.
> +
> + tmp = I915_READ(UTIL_PIN_CTL);
> + tmp |= ICL_UTIL_PIN_DIRECTION;
If the macro had INPUT in the name, this would be self-explanatory.
> + tmp |= UTIL_PIN_ENABLE;
> + I915_WRITE(UTIL_PIN_CTL, tmp);
> +}
> +
> static void
> gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> @@ -974,6 +994,9 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> /* setup D-PHY timings */
> gen11_dsi_setup_dphy_timings(encoder);
>
> + /* Since transcoder is configured to take events from GPIO */
> + gen11_dsi_config_util_pin(encoder);
> +
> /* step 4h: setup DSI protocol timeouts */
> gen11_dsi_setup_timeouts(encoder);
>
> @@ -1104,6 +1127,15 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
> enum transcoder dsi_trans;
> u32 tmp;
>
> + /* disable periodic update mode */
> + if (is_cmd_mode(intel_dsi)) {
> + for_each_dsi_port(port, intel_dsi->ports) {
> + tmp = I915_READ(ICL_DSI_CMD_FRMCTL(port));
> + tmp &= ~ICL_PERIODIC_FRAME_UPDATE_ENABLE;
> + I915_WRITE(ICL_DSI_CMD_FRMCTL(port), tmp);
> + }
> + }
> +
> /* put dsi link in ULPS */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
