Hi
2012/11/5 Daniel Vetter <daniel.vetter at ffwll.ch>:
> A few things needed to change:
> - HAS_PCH_SPLIT since ilk+ is not yet converted to this.
> - s/LVDS/intel_lvds->reg/ to prep for ilk conversion
> - replace the clock.p2 == 7 check with a is_dual_link check
> - s/adjusted_mode/intel_lvds->fixed_mode
>
> v2: Rebase on top of Jani Nikula's panel rework. I'm wondering whether
> we shouldn't add an attached_panel pointer to intel_encoder, to
> replace the encoder private ->attached_connector pointers, since
> that's essentially what we need.
>
> Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 59 ------------------------------------
> drivers/gpu/drm/i915/intel_lvds.c | 57 ++++++++++++++++++++++++++++++++++
> 2 files changed, 57 insertions(+), 59 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 7309790..bd3fa2b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4259,51 +4259,6 @@ static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
> }
> }
>
> -static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
> - struct drm_display_mode *adjusted_mode)
> -{
> - struct drm_device *dev = crtc->dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> - struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> - int pipe = intel_crtc->pipe;
> - u32 temp;
> -
> - temp = I915_READ(LVDS);
> - temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> - if (pipe == 1) {
> - temp |= LVDS_PIPEB_SELECT;
> - } else {
> - temp &= ~LVDS_PIPEB_SELECT;
> - }
> - /* set the corresponsding LVDS_BORDER bit */
> - temp |= dev_priv->lvds_border_bits;
> - /* Set the B0-B3 data pairs corresponding to whether we're going to
> - * set the DPLLs for dual-channel mode or not.
> - */
> - if (clock->p2 == 7)
> - temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> - else
> - temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> -
> - /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> - * appropriately here, but we need to look more thoroughly into how
> - * panels behave in the two modes.
> - */
> - /* set the dithering flag on LVDS as needed */
> - if (INTEL_INFO(dev)->gen >= 4) {
> - if (dev_priv->lvds_dither)
> - temp |= LVDS_ENABLE_DITHER;
> - else
> - temp &= ~LVDS_ENABLE_DITHER;
> - }
> - temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> - if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
> - temp |= LVDS_HSYNC_POLARITY;
> - if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
> - temp |= LVDS_VSYNC_POLARITY;
> - I915_WRITE(LVDS, temp);
> -}
> -
> static void vlv_update_pll(struct drm_crtc *crtc,
> struct drm_display_mode *mode,
> struct drm_display_mode *adjusted_mode,
> @@ -4486,13 +4441,6 @@ static void i9xx_update_pll(struct drm_crtc *crtc,
> if (encoder->pre_pll_enable)
> encoder->pre_pll_enable(encoder);
>
> - /* The LVDS pin pair needs to be on before the DPLLs are enabled.
> - * This is an exception to the general rule that mode_set doesn't turn
> - * things on.
> - */
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> - intel_update_lvds(crtc, clock, adjusted_mode);
> -
> if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
> intel_dp_set_m_n(crtc, mode, adjusted_mode);
>
> @@ -4568,13 +4516,6 @@ static void i8xx_update_pll(struct drm_crtc *crtc,
> if (encoder->pre_pll_enable)
> encoder->pre_pll_enable(encoder);
>
> - /* The LVDS pin pair needs to be on before the DPLLs are enabled.
> - * This is an exception to the general rule that mode_set doesn't turn
> - * things on.
> - */
> - if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
> - intel_update_lvds(crtc, clock, adjusted_mode);
> -
> I915_WRITE(DPLL(pipe), dpll);
>
> /* Wait for the clocks to stabilize. */
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index 972ef12..057e29a 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -89,6 +89,62 @@ static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
> return true;
> }
>
> +/* The LVDS pin pair needs to be on before the DPLLs are enabled.
> + * This is an exception to the general rule that mode_set doesn't turn
> + * things on.
> + */
> +static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
> +{
> + struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
> + struct drm_device *dev = encoder->base.dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> + struct drm_display_mode *fixed_mode =
> + lvds_encoder->attached_connector->base.panel.fixed_mode;
> + int pipe = intel_crtc->pipe;
> + u32 temp;
> +
> + /* pch split platforms are not yet converted. */
> + if (HAS_PCH_SPLIT(dev))
> + return;
> +
> + temp = I915_READ(lvds_encoder->reg);
> + temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
> + if (pipe == 1) {
> + temp |= LVDS_PIPEB_SELECT;
> + } else {
> + temp &= ~LVDS_PIPEB_SELECT;
> + }
> + /* set the corresponsding LVDS_BORDER bit */
> + temp |= dev_priv->lvds_border_bits;
> + /* Set the B0-B3 data pairs corresponding to whether we're going to
> + * set the DPLLs for dual-channel mode or not.
> + */
> + if (lvds_encoder->is_dual_link)
> + temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
> + else
> + temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
> +
> + /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
> + * appropriately here, but we need to look more thoroughly into how
> + * panels behave in the two modes.
> + */
> + /* set the dithering flag on LVDS as needed */
> + if (INTEL_INFO(dev)->gen >= 4) {
> + if (dev_priv->lvds_dither)
> + temp |= LVDS_ENABLE_DITHER;
> + else
> + temp &= ~LVDS_ENABLE_DITHER;
> + }
> + temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
> + if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
> + temp |= LVDS_HSYNC_POLARITY;
> + if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
> + temp |= LVDS_VSYNC_POLARITY;
> +
> + I915_WRITE(lvds_encoder->reg, temp);
> +}
> +
> /**
> * Sets the power state for the panel.
> */
> @@ -1038,6 +1094,7 @@ bool intel_lvds_init(struct drm_device *dev)
> DRM_MODE_ENCODER_LVDS);
>
> intel_encoder->enable = intel_enable_lvds;
> + intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
> intel_encoder->disable = intel_disable_lvds;
> intel_encoder->get_hw_state = intel_lvds_get_hw_state;
> intel_connector->get_hw_state = intel_connector_get_hw_state;
> --
> 1.7.11.7
>
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> Intel-gfx at lists.freedesktop.org
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--
Paulo Zanoni
