On Tue, 06 Nov 2012, Ben Widawsky <ben at bwidawsk.net> wrote:
> This replaces the existing MBOX update code with a more generalized
> calculation for emitting mbox updates. We also create a sentinel for
> doing the updates so we can more abstractly deal with the rings.
>
> When doing MBOX updates the code must be aware of the /other/ rings.
> Until now the platforms which supported semaphores had a fixed number of
> rings and so it made sense for the code to be very specialized
> (hardcoded).
>
> The patch does contain a functional change, but should have no
> behavioral changes.
>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> drivers/gpu/drm/i915/intel_ringbuffer.c | 40 ++++++++++++++++++++-------------
> drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +-
> 3 files changed, 27 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f82755e..d220410 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -438,6 +438,7 @@
> #define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
> #define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
> #define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
> +#define GEN6_NOSYNC 0
> #define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
> #define RING_MAX_IDLE(base) ((base)+0x54)
> #define RING_HWS_PGA(base) ((base)+0x80)
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 423948f..ace1176 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -558,12 +558,14 @@ update_mboxes(struct intel_ring_buffer *ring,
> u32 seqno,
> u32 mmio_offset)
> {
> +#define MBOX_UPDATE_DWORDS 4
> intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
> MI_SEMAPHORE_GLOBAL_GTT |
> MI_SEMAPHORE_REGISTER |
> MI_SEMAPHORE_UPDATE);
> intel_ring_emit(ring, seqno);
> intel_ring_emit(ring, mmio_offset);
> + intel_ring_emit(ring, MI_NOOP);
I take it this is the functional change you refer to in the commit
message, but the reason why is missing.
> }
>
> /**
> @@ -579,21 +581,26 @@ static int
> gen6_add_request(struct intel_ring_buffer *ring,
> u32 *seqno)
> {
> - u32 mbox1_reg;
> - u32 mbox2_reg;
> - int ret;
> + struct drm_device *dev = ring->dev;
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + struct intel_ring_buffer *useless;
> + int i, ret;
>
> - ret = intel_ring_begin(ring, 10);
> + ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
> + MBOX_UPDATE_DWORDS) +
> + 4);
My only (possibly unwarranted) worry about this patch is that this and
the for_each_ring below implicitly expect each ring->signal_mbox to have
*exactly* one GEN6_NOSYNC, and there are no comments or checks about
it. How does it blow up if that is not the case?
Other than the comments above,
Reviewed-by: Jani Nikula <jani.nikula at intel.com>
> if (ret)
> return ret;
> -
> - mbox1_reg = ring->signal_mbox[0];
> - mbox2_reg = ring->signal_mbox[1];
> +#undef MBOX_UPDATE_DWORDS
>
> *seqno = i915_gem_next_request_seqno(ring);
>
> - update_mboxes(ring, *seqno, mbox1_reg);
> - update_mboxes(ring, *seqno, mbox2_reg);
> + for_each_ring(useless, dev_priv, i) {
> + u32 mbox_reg = ring->signal_mbox[i];
> + if (mbox_reg != GEN6_NOSYNC)
> + update_mboxes(ring, *seqno, mbox_reg);
> + }
> +
> intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
> intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
> intel_ring_emit(ring, *seqno);
> @@ -1506,8 +1513,9 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
> - ring->signal_mbox[0] = GEN6_VRSYNC;
> - ring->signal_mbox[1] = GEN6_BRSYNC;
> + ring->signal_mbox[RCS] = GEN6_NOSYNC;
> + ring->signal_mbox[VCS] = GEN6_VRSYNC;
> + ring->signal_mbox[BCS] = GEN6_BRSYNC;
> } else if (IS_GEN5(dev)) {
> ring->add_request = pc_render_add_request;
> ring->flush = gen4_render_ring_flush;
> @@ -1642,8 +1650,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
> - ring->signal_mbox[0] = GEN6_RVSYNC;
> - ring->signal_mbox[1] = GEN6_BVSYNC;
> + ring->signal_mbox[RCS] = GEN6_RVSYNC;
> + ring->signal_mbox[VCS] = GEN6_NOSYNC;
> + ring->signal_mbox[BCS] = GEN6_BVSYNC;
> } else {
> ring->mmio_base = BSD_RING_BASE;
> ring->flush = bsd_ring_flush;
> @@ -1687,8 +1696,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
> ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
> ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
> ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
> - ring->signal_mbox[0] = GEN6_RBSYNC;
> - ring->signal_mbox[1] = GEN6_VBSYNC;
> + ring->signal_mbox[RCS] = GEN6_RBSYNC;
> + ring->signal_mbox[VCS] = GEN6_VBSYNC;
> + ring->signal_mbox[BCS] = GEN6_NOSYNC;
> ring->init = init_ring_common;
>
> return intel_init_ring_buffer(dev, ring);
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
> index df1a0a2..d8eecb1 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.h
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
> @@ -90,7 +90,7 @@ struct intel_ring_buffer {
> u32 seqno);
>
> u32 semaphore_register[I915_NUM_RINGS]; /*our mbox written by others */
> - u32 signal_mbox[2]; /* mboxes this ring signals to */
> + u32 signal_mbox[I915_NUM_RINGS]; /* mboxes this ring signals to */
> /**
> * List of objects currently involved in rendering from the
> * ringbuffer.
> --
> 1.8.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
