On Wed, Oct 31, 2012 at 06:12:48PM -0200, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni at intel.com> > > ... instead of PIPECONF_INTERLACE_MASK. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> My Bspec here still has bits 23:21 for the interlaced bits on the lpt pch, but everything with bit 23 set is a reserved value. Sinc we set the correct stuff anyway, I don't think we need to change the mask here - the same would apply to cpt. So I'll drop this one here. -Daniel > --- > drivers/gpu/drm/i915/intel_display.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 066994f..4fbb296 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -1733,7 +1733,8 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, > pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); > > val &= ~TRANS_INTERLACE_MASK; > - if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) > + if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == > + PIPECONF_INTERLACED_ILK) > val |= TRANS_INTERLACED; > else > val |= TRANS_PROGRESSIVE; > -- > 1.7.11.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch
