Hi
2012/10/31 Damien Lespiau <damien.lespiau at gmail.com>:
> From: Damien Lespiau <damien.lespiau at intel.com>
>
> ILK+ have this register on the PCH. This check was triggering unclaimed
> writes.
>
> Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
The patch looks correct, so:
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
The only problem is: we're not doing anything here for the
HAS_PCH_SPLIT platforms. Shouldn't we be doing something? We do have
eDP code to set the PCH_PP registers, but not LVDS code for this.
Also, each encoder probably needs different values.
So my suggestion would be: apply this patch (since it fixes a problem)
and then, in the future, maybe, move this code to the encoder-specific
callbacks, and also consider the HAS_PCH_SPLIT + LVDS case.
> ---
> drivers/gpu/drm/i915/intel_bios.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
> index 0ed6baf..87e9b92 100644
> --- a/drivers/gpu/drm/i915/intel_bios.c
> +++ b/drivers/gpu/drm/i915/intel_bios.c
> @@ -762,7 +762,8 @@ void intel_setup_bios(struct drm_device *dev)
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> /* Set the Panel Power On/Off timings if uninitialized. */
> - if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {
> + if (!HAS_PCH_SPLIT(dev) &&
> + I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
> /* Set T2 to 40ms and T5 to 200ms */
> I915_WRITE(PP_ON_DELAYS, 0x019007d0);
>
> --
> 1.7.11.7
>
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--
Paulo Zanoni
