On Mon, May 28, 2012 at 04:43:00PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni <paulo.r.zanoni at intel.com> > > On IVB and older, we basically have two registers: the control and the > data register. We write a few consecutitve times to the control > register, and we need these writes to arrive exactly in the specified > order. > > Also, when we're changing the data register, we need to guarantee that > anything written to the control register already arrived (since > changing the control register can change where the data register > points to). Also, we need to make sure all the writes to the data > register happen exactly in the specified order, and we also *can't* > read the data register during this process, since reading and/or > writing it will change the place it points to. > > So invoke the "better safe than sorry" rule and just be careful and > put barriers everywhere :) > > On HSW we still have a control register that we write many times, but > we have many data registers. > > Demanded-by: Chris Wilson <chris at chris-wilson.co.uk> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> Ok, I've all patches from this series for -next safe for the patches 10, 12 and 14: - for 14 I've already dumped a bikeshed - 10 and 12 I like, but I fear we'll get too many merge conflicts against -fixes if I merge them this early. I'd still like to include them for 3.6, so can you please resend these two later in the 3.5 cycle, when things have settled a bit for -fixes? Thanks a lot for digging into this infoframe maze. Cheers, Daniel -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
