2012/5/12 Daniel Vetter <daniel.vetter at ffwll.ch>:
> We've simply ignored this, which isn't too great. With this, interlaced
> 1080i works on my HDMI screen connected through sdvo. For no apparent
> reason anything else still doesn't work as it should.
>
> While at it, give these magic numbers in the dtd proper names and
> add a comment that they match with EDID detailed timings.
>
> v2: Actually use the right bit for interlaced.
>
> Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
This looks like 2 different patches merged into one :)
In theory, bits 2 and 1 could have a different meaning too, but I'm
not sure how applicable this is to sDVO. But yeah, I had to read this
code in the past and 0x2 and 0x4 were not exactly nice to read, so at
least now those bits have a name :)
Not tested, just reviewed against the sdvo and edid specs...
Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> ?drivers/gpu/drm/i915/intel_sdvo.c ? ? ?| ? 12 ++++++++----
> ?drivers/gpu/drm/i915/intel_sdvo_regs.h | ? ?5 +++++
> ?2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 125228e..a658207 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -783,10 +783,12 @@ static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
> ? ? ? ? ? ? ? ?((v_sync_len & 0x30) >> 4);
>
> ? ? ? ?dtd->part2.dtd_flags = 0x18;
> + ? ? ? if (mode->flags & DRM_MODE_FLAG_INTERLACE)
> + ? ? ? ? ? ? ? dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
> ? ? ? ?if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> - ? ? ? ? ? ? ? dtd->part2.dtd_flags |= 0x2;
> + ? ? ? ? ? ? ? dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
> ? ? ? ?if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> - ? ? ? ? ? ? ? dtd->part2.dtd_flags |= 0x4;
> + ? ? ? ? ? ? ? dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
>
> ? ? ? ?dtd->part2.sdvo_flags = 0;
> ? ? ? ?dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
> @@ -820,9 +822,11 @@ static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
> ? ? ? ?mode->clock = dtd->part1.clock * 10;
>
> ? ? ? ?mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
> - ? ? ? if (dtd->part2.dtd_flags & 0x2)
> + ? ? ? if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
> + ? ? ? ? ? ? ? mode->flags |= DRM_MODE_FLAG_INTERLACE;
> + ? ? ? if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
> ? ? ? ? ? ? ? ?mode->flags |= DRM_MODE_FLAG_PHSYNC;
> - ? ? ? if (dtd->part2.dtd_flags & 0x4)
> + ? ? ? if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
> ? ? ? ? ? ? ? ?mode->flags |= DRM_MODE_FLAG_PVSYNC;
> ?}
>
> diff --git a/drivers/gpu/drm/i915/intel_sdvo_regs.h b/drivers/gpu/drm/i915/intel_sdvo_regs.h
> index 6b7b22f..9d03014 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo_regs.h
> +++ b/drivers/gpu/drm/i915/intel_sdvo_regs.h
> @@ -61,6 +61,11 @@ struct intel_sdvo_caps {
> ? ? ? ?u16 output_flags;
> ?} __attribute__((packed));
>
> +/* Note: SDVO detailed timing flags match EDID misc flags. */
> +#define DTD_FLAG_HSYNC_POSITIVE (1 << 1)
> +#define DTD_FLAG_VSYNC_POSITIVE (1 << 2)
> +#define DTD_FLAG_INTERLACE ? ? (1 << 7)
> +
> ?/** This matches the EDID DTD structure, more or less */
> ?struct intel_sdvo_dtd {
> ? ? ? ?struct {
> --
> 1.7.8.3
>
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--
Paulo Zanoni
