On Sun, 20 May 2012 18:55:09 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > This should fix breakage introduced in > > commit ee7b9f93fd96a72e5d09e2b44024c11880873c6b > Author: Jesse Barnes <jbarnes at virtuousgeek.org> > Date: Fri Apr 20 17:11:53 2012 +0100 > > drm/i915: manage PCH PLLs separately from pipes > > Cc: Jesse Barnes <jbarnes at virtuousgeek.org> > Cc: Chris Wilson <chris at chris-wilson.co.uk> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=49712 > Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch> > --- > drivers/gpu/drm/i915/intel_display.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index f3d39f4..f4b2ce9 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2911,6 +2911,14 @@ static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u3 > goto prepare; > } > > + if (HAS_PCH_IBX(dev_priv->dev)) { Aside from the debate we had whether HAS_PCH_IBX or !HAS_PCH_CPT was more appropriate considering the later switching on HAS_PCH_CPT for selectable DPLLs... > + /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ > + i = intel_crtc->pipe; > + pll = &dev_priv->pch_plls[i]; DRM_DEBUG_KMS("CRTC:%d pre-allocated PCH PLL %x\n", intel_crtc->base.base.id, pll->pll_reg); so that we have a consistent DEBUG story along all paths. I should have spotted that much earlier, Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> -Chris -- Chris Wilson, Intel Open Source Technology Centre
