On Sun, 13 May 2012 09:54:09 +0100 Chris Wilson <chris at chris-wilson.co.uk> wrote: > Hidden away within one chipset specific path was the necessary logic to > turn on the PLL. This needs to be done everywhere in order for us to > drive any display! As such as soon as we tested on a non-CougarPoint > chipset, we failed to bring up any DisplayPorts and generated a nice set > of assertion failures in the process. At least one part of our logic is > working, the part that assumes that we have no idea what we are doing. > > Reported-by: guang.a.yang at intel.com > References: https://bugs.freedesktop.org/show_bug.cgi?id=49712 > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Cc: Jesse Barnes <jbarnes at virtuousgeek.org> > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a679a9a..d0112ec 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -2887,14 +2887,14 @@ static void ironlake_pch_enable(struct drm_crtc *crtc) > /* For PCH output, training FDI link */ > dev_priv->display.fdi_link_train(crtc); > > + intel_enable_pch_pll(intel_crtc); > + > if (HAS_PCH_LPT(dev)) { > DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n"); > lpt_program_iclkip(crtc); > } else if (HAS_PCH_CPT(dev)) { > u32 sel; > > - intel_enable_pch_pll(intel_crtc); > - > temp = I915_READ(PCH_DPLL_SEL); > switch (pipe) { > default: Thanks Chris. Only thing I'm not sure about is the LPT bit; does this function do what we want there? Other than that: Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org> Thanks, -- Jesse Barnes, Intel Open Source Technology Center
