== Series Details == Series: Initial support for Tiger Lake URL : https://patchwork.freedesktop.org/series/62726/ State : warning == Summary == $ dim checkpatch origin/drm-tip 11acbbf944b4 drm/i915: Add modular FIA 68a37855e4a8 drm/i915: rework reading pipe disable fuses 8deb258dbdfa drm/i915: Add 4th pipe and transcoder 97e5552d3dda drm/i915/tgl: add initial Tiger Lake definitions d37ae0840709 drm/i915/tgl: Introduce Tiger Lake PCH 3fd4f1dc5286 drm/i915/tgl: Add TGL PCH detection in virtualized environment 766b92a4b2f2 drm/i915/tgl: Add TGL PCI IDs -:32: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses #32: FILE: include/drm/i915_pciids.h:586: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) -:32: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'info' - possible side-effects? #32: FILE: include/drm/i915_pciids.h:586: +#define INTEL_TGL_12_IDS(info) \ + INTEL_VGA_DEVICE(0x9A49, info), \ + INTEL_VGA_DEVICE(0x9A40, info), \ + INTEL_VGA_DEVICE(0x9A59, info), \ + INTEL_VGA_DEVICE(0x9A60, info), \ + INTEL_VGA_DEVICE(0x9A68, info), \ + INTEL_VGA_DEVICE(0x9A70, info), \ + INTEL_VGA_DEVICE(0x9A78, info) total: 1 errors, 0 warnings, 1 checks, 21 lines checked 395ace571e5f x86/gpu: add TGL stolen memory support 8970927b20d1 drm/i915/tgl: Check if pipe D is fused 66ee79950737 drm/i915/tgl: Add power well support 4f73b6dd1f06 drm/i915/tgl: Add power well to support 4th pipe 6385567b0fae drm/i915/tgl: Add TRANSCODER_A_VDSC power domain 0f07f1b15921 drm/i915/tgl: Add new pll ids 3832dc4784d1 drm/i915/tgl: Add pll manager 288f822662c0 drm/i915/tgl: Add additional ports for Tiger Lake 30da2d6e342c drm/i915/tgl: update ddi/tc clock_off bits -:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects? #24: FILE: drivers/gpu/drm/i915/i915_reg.h:9711: +#define ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(port) (1 << ((port) == PORT_C ? 24 : \ + (port) + 10)) -:26: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'tc_port' - possible side-effects? #26: FILE: drivers/gpu/drm/i915/i915_reg.h:9713: +#define ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port) (1 << ((tc_port) < PORT_TC4 ? \ + (tc_port) + 12 : \ + (tc_port) - PORT_TC4 + 21)) total: 0 errors, 0 warnings, 2 checks, 14 lines checked 222d322189e1 drm/i915/tgl: Add gmbus gpio pin to port mapping 1c10181bd3f8 drm/i915/tgl: port to ddc pin mapping f478ac4c8a3b drm/i915/tgl: select correct bit for port select 01cf9f0351e2 drm/i915/tgl: Add third combophy offset aaa5baacdec1 drm/i915/tgl: extend intel_port_is_combophy/tc a62421eb814e drm/i915/tgl: init ddi port A-C for Tiger Lake 233d6f91e009 drm/i915/tgl: Add vbt value mapping for DDC Bus pin ca7dac50ecf6 drm/i915/tgl: apply Display WA #1178 to fix type C dongles e6fa903800d4 drm/i915/gen12: MBUS B credit change 848e93a32472 drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization 5acfca8cab42 drm/i915/tgl: Add DPLL registers a2fb3635e01b drm/i915/tgl: Update DPLL clock reference register _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
