On Wed, May 09, 2012 at 08:29:57PM -0300, Eugeni Dodonov wrote:
> This attempts to enable all the available power wells during the
> initialization.
>
> Those power wells can be enabled in parallel or on-demand, and disabled
> when no longer needed, but this is out of scope of this initial
> enablement. Proper tracking of who uses which power well will require
> a considerable rework of our display handling, so we just leave them all
> enabled when the driver is loaded for now.
>
> v2: use more generic and future-proof code
>
> v3: call intel_init_power_wells from within intel_modeset_init_hw, so it
> would be called upon resume path as well.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
I've picked up everything up to this one here into dinq. Can you please
double-check whether the power well enabling is still at the right place?
I've somehow dropped Chris' patch to move around things for the rps stuff
that I've merged yesterday, but now it's back as:
commit 2e1352cf196094f44e73776f41087f4c489ab936
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date: Wed May 9 11:56:28 2012 +0100
drm/i915: gen6_enable_rps() wants to be called after ring
initialisation
Cheers, Daniel
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +++++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 31 +++++++++++++++++++++++++++++++
> 3 files changed, 39 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 549cc3f..a40888b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6738,6 +6738,13 @@ void intel_modeset_init_hw(struct drm_device *dev)
>
> if (IS_IVYBRIDGE(dev))
> ivb_pch_pwm_override(dev);
> +
> + if (IS_HASWELL(dev)) {
> + /* We attempt to init the necessary power wells early in the initialization
> + * time, so the subsystems that expect power to be enabled can work.
> + */
> + intel_init_power_wells(dev);
> + }
> }
>
> void intel_modeset_init(struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index e5ee166..8b2b2dd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -443,6 +443,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
>
> extern void intel_init_clock_gating(struct drm_device *dev);
> +extern void intel_init_power_wells(struct drm_device *dev);
> extern void intel_write_eld(struct drm_encoder *encoder,
> struct drm_display_mode *mode);
> extern void intel_cpt_verify_modeset(struct drm_device *dev, int pipe);
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 21587f8..dd9e815 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3559,6 +3559,37 @@ void intel_sanitize_pm(struct drm_device *dev)
> dev_priv->display.sanitize_pm(dev);
> }
>
> +/* Starting with Haswell, we have different power wells for
> + * different parts of the GPU. This attempts to enable them all.
> + */
> +void intel_init_power_wells(struct drm_device *dev)
> +{
> + struct drm_i915_private *dev_priv = dev->dev_private;
> + unsigned long power_wells[] = {
> + HSW_PWR_WELL_CTL1,
> + HSW_PWR_WELL_CTL2,
> + HSW_PWR_WELL_CTL4
> + };
> + int i;
> +
> + if (!IS_HASWELL(dev))
> + return;
> +
> + mutex_lock(&dev->struct_mutex);
> +
> + for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
> + int well = I915_READ(power_wells[i]);
> +
> + if ((well & HSW_PWR_WELL_STATE) == 0) {
> + I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
> + if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
> + DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
> + }
> + }
> +
> + mutex_unlock(&dev->struct_mutex);
> +}
> +
> /* Set up chip specific power management-related functions */
> void intel_init_pm(struct drm_device *dev)
> {
> --
> 1.7.10
>
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> Intel-gfx at lists.freedesktop.org
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--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
