For now, only print their content for diffing, but also add the necessary
bits that can be used for more verbose output in the fugure.
Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
---
lib/intel_reg.h | 157 ++++++++++++++++++++++++++++++++++++++++++++++
tools/intel_reg_dumper.c | 68 ++++++++++++++++++++
2 files changed, 225 insertions(+)
diff --git a/lib/intel_reg.h b/lib/intel_reg.h
index 427efee..a92d26f 100644
--- a/lib/intel_reg.h
+++ b/lib/intel_reg.h
@@ -3542,4 +3542,161 @@ typedef enum {
#define GEN6_RC6pp_THRESHOLD 0xA0C0
#define GEN6_PMINTRMSK 0xA168
+/* Haswell-related items */
+
+/* HSW Power Wells */
+#define HSW_PWR_WELL_CTL1 0x45400 /* BIOS */
+#define HSW_PWR_WELL_CTL2 0x45404 /* Driver */
+#define HSW_PWR_WELL_CTL3 0x45408 /* KVMR */
+#define HSW_PWR_WELL_CTL4 0x4540C /* Debug */
+#define HSW_PWR_WELL_ENABLE (1<<31)
+#define HSW_PWR_WELL_STATE (1<<30)
+#define HSW_PWR_WELL_CTL5 0x45410
+#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
+#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
+#define HSW_PWR_WELL_FORCE_ON (1<<19)
+#define HSW_PWR_WELL_CTL6 0x45414
+
+/* Per-pipe DDI Function Control */
+#define PIPE_DDI_FUNC_CTL_A 0x60400
+#define PIPE_DDI_FUNC_CTL_B 0x61400
+#define PIPE_DDI_FUNC_CTL_C 0x62400
+#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
+#define DDI_FUNC_CTL(pipe) _PIPE(pipe, \
+ PIPE_DDI_FUNC_CTL_A, \
+ PIPE_DDI_FUNC_CTL_B)
+#define PIPE_DDI_FUNC_ENABLE (1<<31)
+/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
+#define PIPE_DDI_PORT_MASK (0xf<<28)
+#define PIPE_DDI_SELECT_PORT(x) ((x)<<28)
+#define PIPE_DDI_MODE_SELECT_HDMI (0<<24)
+#define PIPE_DDI_MODE_SELECT_DVI (1<<24)
+#define PIPE_DDI_MODE_SELECT_DP_SST (2<<24)
+#define PIPE_DDI_MODE_SELECT_DP_MST (3<<24)
+#define PIPE_DDI_MODE_SELECT_FDI (4<<24)
+#define PIPE_DDI_BPC_8 (0<<20)
+#define PIPE_DDI_BPC_10 (1<<20)
+#define PIPE_DDI_BPC_6 (2<<20)
+#define PIPE_DDI_BPC_12 (3<<20)
+#define PIPE_DDI_BFI_ENABLE (1<<4)
+#define PIPE_DDI_PORT_WIDTH_X1 (0<<1)
+#define PIPE_DDI_PORT_WIDTH_X2 (1<<1)
+#define PIPE_DDI_PORT_WIDTH_X4 (3<<1)
+
+/* DisplayPort Transport Control */
+#define DP_TP_CTL_A 0x64040
+#define DP_TP_CTL_B 0x64140
+#define DP_TP_CTL_C 0x64240
+#define DP_TP_CTL_D 0x64340
+#define DP_TP_CTL_E 0x64440
+#define DP_TP_CTL_ENABLE (1<<31)
+#define DP_TP_CTL_MODE_SST (0<<27)
+#define DP_TP_CTL_MODE_MST (1<<27)
+#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
+#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
+#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
+#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
+#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
+#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
+
+/* DisplayPort Transport Status */
+#define DP_TP_STATUS_A 0x64044
+#define DP_TP_STATUS_B 0x64144
+#define DP_TP_STATUS_C 0x64244
+#define DP_TP_STATUS_D 0x64344
+#define DP_TP_STATUS_E 0x64444
+#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
+
+/* DDI Buffer Control */
+#define DDI_BUF_CTL_A 0x64000
+#define DDI_BUF_CTL_B 0x64100
+#define DDI_BUF_CTL_C 0x64200
+#define DDI_BUF_CTL_D 0x64300
+#define DDI_BUF_CTL_E 0x64400
+#define DDI_BUF_CTL_ENABLE (1<<31)
+#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
+#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
+#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
+#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
+#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
+#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
+#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
+#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
+#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
+#define DDI_BUF_EMP_MASK (0xf<<24)
+#define DDI_BUF_IS_IDLE (1<<7)
+#define DDI_PORT_WIDTH_X1 (0<<1)
+#define DDI_PORT_WIDTH_X2 (1<<1)
+#define DDI_PORT_WIDTH_X4 (3<<1)
+#define DDI_INIT_DISPLAY_DETECTED (1<<0)
+
+/* LPT PIXCLK_GATE */
+#define PIXCLK_GATE 0xC6020
+#define PIXCLK_GATE_UNGATE 1<<0
+#define PIXCLK_GATE_GATE 0<<0
+
+/* SPLL */
+#define SPLL_CTL 0x46020
+#define SPLL_PLL_ENABLE (1<<31)
+#define SPLL_PLL_SCC (1<<28)
+#define SPLL_PLL_NON_SCC (2<<28)
+#define SPLL_PLL_FREQ_810MHz (0<<26)
+#define SPLL_PLL_FREQ_1350MHz (1<<26)
+
+/* WRPLL */
+#define WRPLL_CTL1 0x46040
+#define WRPLL_CTL2 0x46060
+#define WRPLL_PLL_ENABLE (1<<31)
+#define WRPLL_PLL_SELECT_SSC (0x01<<28)
+#define WRPLL_PLL_SELECT_NON_SCC (0x02<<28)
+#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
+/* WRPLL divider programming */
+#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
+#define WRPLL_DIVIDER_POST(x) ((x)<<8)
+#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
+
+/* Port clock selection */
+#define PORT_CLK_SEL_A 0x46100
+#define PORT_CLK_SEL_B 0x46104
+#define PORT_CLK_SEL_C 0x46108
+#define PORT_CLK_SEL_D 0x4610C
+#define PORT_CLK_SEL_E 0x46110
+#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
+#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
+#define PORT_CLK_SEL_LCPLL_810 (2<<29)
+#define PORT_CLK_SEL_SPLL (3<<29)
+#define PORT_CLK_SEL_WRPLL1 (4<<29)
+#define PORT_CLK_SEL_WRPLL2 (5<<29)
+
+/* Pipe clock selection */
+#define PIPE_CLK_SEL_A 0x46140
+#define PIPE_CLK_SEL_B 0x46144
+#define PIPE_CLK_SEL_C 0x46148
+/* For each pipe, we need to select the corresponding port clock */
+#define PIPE_CLK_SEL_DISABLED (0x0<<29)
+#define PIPE_CLK_SEL_PORT(x) ((x+1)<<29)
+
+/* LCPLL Control */
+#define LCPLL_CTL 0x130040
+#define LCPLL_PLL_DISABLE (1<<31)
+#define LCPLL_PLL_LOCK (1<<30)
+#define LCPLL_CD_CLOCK_DISABLE (1<<25)
+#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
+
+/* Pipe WM_LINETIME - watermark line time */
+#define PIPE_WM_LINETIME_A 0x45270
+#define PIPE_WM_LINETIME_B 0x45274
+#define PIPE_WM_LINETIME_C 0x45278
+#define PIPE_WM_LINETIME_MASK (0x1ff)
+#define PIPE_WM_LINETIME_TIME(x) ((x))
+#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
+#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
+
+/* SFUSE_STRAP */
+#define SFUSE_STRAP 0xc2014
+#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
+#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
+#define SFUSE_STRAP_DDID_DETECTED (1<<0)
+
+
#endif /* _I810_REG_H */
diff --git a/tools/intel_reg_dumper.c b/tools/intel_reg_dumper.c
index 9f281eb..910d7c1 100644
--- a/tools/intel_reg_dumper.c
+++ b/tools/intel_reg_dumper.c
@@ -1781,6 +1781,71 @@ static struct reg_debug ironlake_debug_regs[] = {
DEFINEREG(RC6pp_RESIDENCY_TIME),
};
+static struct reg_debug haswell_debug_regs[] = {
+ /* Power wells */
+ DEFINEREG(HSW_PWR_WELL_CTL1),
+ DEFINEREG(HSW_PWR_WELL_CTL2),
+ DEFINEREG(HSW_PWR_WELL_CTL3),
+ DEFINEREG(HSW_PWR_WELL_CTL4),
+ DEFINEREG(HSW_PWR_WELL_CTL5),
+ DEFINEREG(HSW_PWR_WELL_CTL6),
+
+ /* DDI pipe function */
+ DEFINEREG(PIPE_DDI_FUNC_CTL_A),
+ DEFINEREG(PIPE_DDI_FUNC_CTL_B),
+ DEFINEREG(PIPE_DDI_FUNC_CTL_C),
+ DEFINEREG(PIPE_DDI_FUNC_CTL_EDP),
+
+ /* DP transport control */
+ DEFINEREG(DP_TP_CTL_A),
+ DEFINEREG(DP_TP_CTL_B),
+ DEFINEREG(DP_TP_CTL_C),
+ DEFINEREG(DP_TP_CTL_D),
+ DEFINEREG(DP_TP_CTL_E),
+
+ /* DP status */
+ DEFINEREG(DP_TP_STATUS_A),
+ DEFINEREG(DP_TP_STATUS_B),
+ DEFINEREG(DP_TP_STATUS_C),
+ DEFINEREG(DP_TP_STATUS_D),
+ DEFINEREG(DP_TP_STATUS_E),
+
+ /* DDI buffer control */
+ DEFINEREG(DDI_BUF_CTL_A),
+ DEFINEREG(DDI_BUF_CTL_B),
+ DEFINEREG(DDI_BUF_CTL_C),
+ DEFINEREG(DDI_BUF_CTL_D),
+ DEFINEREG(DDI_BUF_CTL_E),
+
+ /* Clocks */
+ DEFINEREG(PIXCLK_GATE),
+ DEFINEREG(SPLL_CTL),
+ DEFINEREG(LCPLL_CTL),
+ DEFINEREG(WRPLL_CTL1),
+ DEFINEREG(WRPLL_CTL2),
+
+ /* DDI port clock control */
+ DEFINEREG(PORT_CLK_SEL_A),
+ DEFINEREG(PORT_CLK_SEL_B),
+ DEFINEREG(PORT_CLK_SEL_C),
+ DEFINEREG(PORT_CLK_SEL_D),
+ DEFINEREG(PORT_CLK_SEL_E),
+
+ /* Pipe clock control */
+ DEFINEREG(PIPE_CLK_SEL_A),
+ DEFINEREG(PIPE_CLK_SEL_B),
+ DEFINEREG(PIPE_CLK_SEL_C),
+
+ /* Pipe line time */
+ DEFINEREG(PIPE_WM_LINETIME_A),
+ DEFINEREG(PIPE_WM_LINETIME_B),
+ DEFINEREG(PIPE_WM_LINETIME_C),
+
+ /* Fuses */
+ DEFINEREG(SFUSE_STRAP),
+
+};
+
static struct reg_debug i945gm_mi_regs[] = {
DEFINEREG(PGETBL_CTL),
DEFINEREG(PGTBL_ER),
@@ -2117,5 +2182,8 @@ int main(int argc, char** argv)
if (IS_GEN6(devid) || IS_GEN7(devid))
intel_dump_regs(gen6_rp_debug_regs);
+ if (IS_HASWELL(devid))
+ intel_dump_regs(haswell_debug_regs);
+
return 0;
}
--
1.7.10
