On Fri, Jun 14, 2019 at 02:37:49PM -0700, José Roberto de Souza wrote:
> EHL can have up to one VECS(video enhancement) engine, so add it to
> the device_info.
Bspec 29150 has a footnote on VEbox that indicates "Pass-through only,
no VEbox processing logic." That note seems a bit vague, but I think I
saw some more detailed info in the past somewhere that indicated the
VECS command streamer is still technically present but doesn't actually
do any video enhancement on EHL; it just passes content through to SFC.
I'm not terribly plugged into the media side of the world, so I'm not
sure if we want to expose VECS to userspace if it's basically a noop and
doesn't do what it normally does on other platforms. Bspec page 5229
implies that SFC can be fed directly by the decode engine without going
through VEBOX, so I'm not sure if media userspace would ever have a use
for the passthrough-only VECS streamer.
We should probably ask someone on the media team what their thoughts are
on this.
Matt
>
> BSpec: 29152
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Bob Paauwe <bob.j.paauwe@xxxxxxxxx>
> Cc: Matt Roper <matthew.d.roper@xxxxxxxxx>
> Cc: Clint Taylor <Clinton.A.Taylor@xxxxxxxxx>
> Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 482f1d0f1770..2c5f64ccadb5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -760,7 +760,7 @@ static const struct intel_device_info intel_elkhartlake_info = {
> GEN11_FEATURES,
> PLATFORM(INTEL_ELKHARTLAKE),
> .require_force_probe = 1,
> - .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0),
> + .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VCS0) | BIT(VECS0),
> .ppgtt_size = 36,
> };
>
> --
> 2.22.0
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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