From: Paulo Zanoni <paulo.r.zanoni at intel.com> Make sure we're doing the right thing, just like we do on gen5+. Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com> --- drivers/gpu/drm/i915/intel_hdmi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 612d9ed..397299b 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -146,7 +146,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, else return; - val &= ~VIDEO_DIP_SELECT_MASK; + val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= intel_infoframe_index(frame); val |= VIDEO_DIP_ENABLE; -- 1.7.10
