On Wed, Mar 21, 2012 at 05:19:13PM -0700, Ben Widawsky wrote:
> In theory this will have performance and power improvements. Performance
> because we don't need to stall when the scanout BO is busy, and power
> because we don't have to stall when the BO is busy ie. we can get the
> work done sooner and put the CPU to sleep (and one less interrupt
> required).
>
> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ce2fee5..96ad162 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3041,9 +3041,7 @@ int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
> * any flushes to be pipelined (for pageflips).
> *
> * For the display plane, we want to be in the GTT but out of any write
> - * domains. So in many ways this looks like set_to_gtt_domain() apart from the
> - * ability to pipeline the waits, pinning and any additional subtleties
> - * that may differentiate the display plane from ordinary buffers.
> + * domains. So in many ways this looks like set_to_gtt_domain().
> */
For the comment bikeshed, what about:
"Prepare buffer for display plane (scanout, cursors, etc).
Can be called from an uninterruptible phase (modesetting).
"For display planes we need to flush, synchronize with any outstanding
rendering (pipelined using semaphores, if available, in case of a
pageflip) and additionally need to ensure that the cache_level is coherent
for the scanout engine."
Cheers, Daniel
> int
> i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> @@ -3058,8 +3056,8 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> return ret;
>
> if (pipelined != obj->ring) {
> - ret = i915_gem_object_wait_rendering(obj);
> - if (ret == -ERESTARTSYS)
> + ret = i915_gem_object_sync(obj, pipelined);
> + if (ret)
> return ret;
> }
>
> --
> 1.7.9.4
>
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--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
