On Fri, Mar 30, 2012 at 09:33:22AM +0100, Chris Wilson wrote: > On Thu, 29 Mar 2012 19:11:26 -0700, Ben Widawsky <ben at bwidawsk.net> wrote: > > - gen6 put/get only need one argument > > rflags and gflags are always the same (see above explanation) > > - remove a couple redundantly defined IRQs > > - reordered some lines to make things go in descending order > > > > Every ring has its own interrupts, enables, masks, and status bits that > > are fed into the main interrupt enable/mask/status registers. At one > > point in time it seemed like a good idea to make our functions support > > the notion that each interrupt may have a different bit position in the > > corresponding register (blitter parser error may be bit n in IMR, but > > bit m in blitter IMR). It turned out though that the HW designers did us > > a solid on Gen6+ and this unfortunate situation has been avoided. This > > allows our interrupt code to be cleaned up a bit. > > > > I jammed this into one commit because there should be no functional > > change with this commit, and staging it into multiple commits was > > unnecessarily artificial IMO. > > > > CC: Chris Wilson <chris at chris-wilson.co.uk> > > CC: Jesse Barnes <jbarnes at virtuousgeek.org> > > Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com> > > Those two patches are > Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> Both patches applied, with a few things added to i915_reg.h for the first one - I got confused about this stuff too much. Thanks for wrestling that red dragon. -Daniel -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
