Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov at intel.com> wrote:
> Some double-buffered registers need to be written twice.
>
> Note that it is being sent as a separate patch because sometimes these
> registers do work when written only once. But double-writing on my machine
> ensured that they work more often.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
> ?drivers/gpu/drm/i915/intel_display.c | ? 12 ++++++++----
> ?1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 04625d5..8a839be 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2769,12 +2769,16 @@ static void hsw_fdi_link_train(struct drm_crtc *crtc)
> ? ? ? ?struct drm_i915_private *dev_priv = dev->dev_private;
> ? ? ? ?struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> ? ? ? ?int pipe = intel_crtc->pipe;
> - ? ? ? u32 reg, temp, i;
> + ? ? ? u32 reg, temp, i, j;
>
> ? ? ? ?/* Prior to enabling DDI, configure buffer translation with FDI values */
> - ? ? ? for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
> - ? ? ? ? ? ? ? I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
> - ? ? ? ? ? ? ? reg += 4;
> + ? ? ? /* Those registers seem to be double-buffered - at least, the hw team writes them twice. */
> + ? ? ? for (j=0; j < 2; j++) {
> + ? ? ? ? ? ? ? for (i=0, reg=DDI_BUF_TRANS_E; i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) {
> + ? ? ? ? ? ? ? ? ? ? ? I915_WRITE(reg, hsw_ddi_translations_fdi[i]);
> + ? ? ? ? ? ? ? ? ? ? ? reg += 4;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? udelay(20);
> ? ? ? ?}
>
> ? ? ? ?/* Configure CPU PLL, wait for warmup */
> --
> 1.7.9.2
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net
